Scalable FIR Filter Matrix for Reconfigurable DSP Throughput
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Solution Overview
Problem
Current digital signal processing (DSP) applications face challenges with Finite Impulse Response (FIR) filters, particularly in terms of flexibility, cost-effectiveness, and efficiency, as existing ASICs are inflexible and costly to design, while FPGAs are inefficient in terms of size, weight, and power consumption.
Innovation Solution
A Scalable Finite Impulse Response (SFIR) filter design that includes a pre-processing section, a post-processing section, and a finite impulse response filtering matrix with re-configurable data throughput, integrated into an Application Specific Integrated Circuit (ASIC), allowing for flexible configuration and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional ASICs are used for FIR filters, then manufacturing efficiency and resource utilization are improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The FIR filter is divided into multiple filter taps arranged in a matrix structure, where each tap can be independently configured. This segmentation allows the same hardware structure to be reconfigured for different filter lengths and specifications, achieving both manufacturing efficiency through standardized production and flexibility through programmable configuration of individual taps.
Solution Approach 2:
The patent creates a universal filter matrix structure that can perform multiple different FIR filter functions by reconfiguring the connections and activation of filter taps. The same physical hardware can be programmed to implement various filter lengths, coefficients, and specifications, eliminating the need for separate ASIC designs for different filter requirements.
2Adaptability or versatility
If FPGAs are used for FIR filters, then flexibility and adaptability are improved, but size, weight, and power consumption worsen
Solution Approach 1:
The patent implements a dynamic reconfiguration capability within a fixed ASIC structure, allowing the filter to adapt its behavior through programmable control of filter tap activations and connections. This provides FPGA-like flexibility while maintaining the compact, efficient physical footprint of an ASIC, significantly reducing size, weight, and power compared to FPGA implementations.
3Reliability
If larger filter sizes are used, then filtering performance is improved, but manufacturing difficulty and complexity worsen
Solution Approach 1:
The patent employs a nested matrix structure where filter taps are arranged in rows and columns, allowing larger filter configurations to be built by activating more taps within the same physical structure. This nested arrangement enables scalable filter performance without proportionally increasing manufacturing complexity, as the same modular tap units are reused in different configurations.
Data Source
AI summary
A Scalable Finite Impulse Response (“SFIR”) filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.