Scalable Glitch Modeling for Accurate Power Estimation
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Solution Overview
Problem
Conventional digital simulation tools for pre-silicon power consumption estimation in IC design fail to accurately model glitch power contributions, leading to inaccuracies in power consumption predictions and increased manufacturing costs due to overly simplified glitch modeling techniques that either filter or propagate glitches entirely, without considering cell-type-specific decaying effects.
Innovation Solution
A computer-implemented method for scalable glitch modeling that involves determining the input duration of glitches, assigning cell-type-specific scaling factors, and controlling the output duration to accurately model glitch decaying effects, thereby reducing the duration of outgoing glitches and improving toggle count accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional simulation tools filter or propagate glitches entirely, then the simulation process is simple, but the power consumption estimation accuracy deteriorates
Solution Approach 1:
The patent applies parameter changes by introducing cell-type-specific scaling factors that modify glitch duration based on the receiving cell's characteristics. Instead of uniformly filtering or propagating all glitches, the simulation tool dynamically adjusts glitch parameters (duration and strength) according to the specific cell type receiving the glitch, thereby achieving accurate power consumption estimation without excessive complexity.
Solution Approach 2:
The patent implements local quality by making glitch propagation behavior dependent on the specific cell type receiving the glitch. Different cell types (e.g., latches, flip-flops, logic gates) have different glitch susceptibility and decaying characteristics. The simulation tool applies different scaling factors to glitches based on the receiving cell's local properties, rather than applying a universal glitch handling rule throughout the circuit.
2Measurement precision
If traditional circuit design simulation techniques are used, then power consumption estimation accuracy is improved, but runtime and memory capacity requirements increase
Solution Approach 1:
The patent applies partial action by selectively modeling only the most significant glitch effects on power consumption rather than performing complete traditional circuit simulation. The glitch scaling approach focuses computational resources on capturing the dominant glitch-induced power consumption patterns using simplified models, achieving acceptable accuracy without the full computational burden of traditional simulation techniques.
3Productivity
If simplified glitch modeling is used, then simulation speed is improved, but toggle count accuracy deteriorates
Solution Approach 1:
The patent changes the parameter representation of glitches by using scaling factors that capture the essential impact of glitches on toggle counts without requiring detailed waveform analysis. Instead of simulating every glitch waveform in detail, the tool uses scaled duration and strength parameters that approximate the net effect on toggle counting, maintaining simulation speed while improving accuracy.
Data Source
AI summary
Glitch propagation is modelled during circuit design simulation by determining the input duration of each signal pulse received by a cell, utilizing the input duration to distinguish whether the input pulse is a glitch or a valid data signal pulse, assigning a cell-type-specific scaling factor value to each signal pulse identified as a scalable glitch, calculating a scheduled output duration by multiplying the scaling factor value and the input duration, and controlling the cell by scaling (i.e., limiting or reducing) the duration of a corresponding output pulse signal to the scheduled output duration. Each cell-type-specific scaling factor value corresponds to observed glitch decaying effect characteristics of corresponding cells in physical IC devices. A simulation tool automatically assigns glitch scaling modules to each cell of a circuit design, whereby the glitch scaling process is performed on each cell during simulation.