Scalable Centralized Error Queues for GPU Fault Logging

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in detecting, logging, and correcting errors efficiently, especially in parallel processing architectures, which are crucial for applications like artificial intelligence and machine learning, where hardware resiliency is essential for reliability and availability.

Innovation Solution

Implementing scalable centralized error queues within the GPU architecture to detect, log, and report errors effectively, enabling better error handling and recovery mechanisms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel processing architectures are used to increase processing throughput, then productivity is improved, but reliability deteriorates due to increased error detection and handling challenges

Engineering Contradiction:

Improveprocessing throughputVSAvoiderror detection capability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The error queue is divided into multiple segments or banks, with each processing element having dedicated error queue entries. This segmentation allows parallel error tracking without requiring a single centralized error handling mechanism, thus maintaining both high throughput and reliable error detection in SIMD/SIMT architectures.

Inventive Principle:

Principle #1Segmentation

2Reliability

If centralized error queues are implemented to improve error handling, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveerror handling capabilityVSAvoiderror queue structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The error queue structure is designed to serve multiple processing elements simultaneously while maintaining a unified interface. The same error queue mechanism handles errors from different processing elements, making the system more reliable without proportionally increasing complexity, as the error handling logic is reused across multiple elements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Error queue entries are nested within processing element contexts, allowing each processing element to have its error state embedded within the broader error queue structure. This nesting enables compact representation of error information without requiring separate complex structures for each processing element.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Reliability

If error detection and logging mechanisms are enhanced, then reliability is improved, but loss of time increases due to additional processing overhead

Engineering Contradiction:

Improveerror detection accuracyVSAvoiderror handling overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Error detection and logging are performed as preliminary actions during the normal processing flow, rather than as separate post-processing steps. Error bits are captured and logged in the error queue concurrently with data processing, eliminating the need for additional time-consuming error checking phases and maintaining both accuracy and efficiency.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250209010A1Scalable centralized error queues in a processing architecture

Publication Date: 2025.06.26 INTEL CORP

AI summary

An apparatus to facilitate scalable centralized error queues in a processing architecture is disclosed. The apparatus includes a processor comprising a systems interface hosting an error aggregator, wherein the processor is to host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processor; receive an error reporting message from a component of the components of the processor, the error reporting message corresponding to an error detected by the component; and log the error as an entry in the at least one centralized error queue based on an error type of the error.