Scalable Hardware Architecture Template for Streaming Data
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Solution Overview
Problem
Existing hardware components struggle to efficiently process streaming input data with varying frame sizes and arrival rates, leading to backpressure and inefficiencies, especially in edge devices with power and resource constraints.
Innovation Solution
A scalable hardware architecture template is used to generate design parameters for machine learning processors, allowing for customization and instantiation of hardware components that can efficiently process streaming input data by determining optimal quantities of clusters, processing units, and hardware unit arrays based on data characteristics, reducing backpressure and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed hardware architecture is used, then manufacturing is simple, but it cannot adapt to varying streaming data characteristics causing backpressure and inefficiency
Solution Approach 1:
The patent implements a dynamic hardware architecture where the quantity of processing units and hardware unit arrays can be configured based on streaming data characteristics. The system transitions from a fixed architecture to a configurable one where design parameters (number of clusters, processing units per cluster, hardware unit arrays per processing unit) are adjusted to match actual data requirements, enabling adaptation without requiring complete hardware redesign.
Solution Approach 2:
The patent changes hardware architecture parameters such as the number of clusters, processing units per cluster, and hardware unit arrays per processing unit based on streaming data characteristics. This allows the same hardware template to produce different architectures optimized for varying data rates, frame sizes, and computational requirements, resolving the contradiction between adaptability and complexity.
2Productivity
If more processing units are added to handle high data rates, then throughput increases, but power consumption and device size increase
Solution Approach 1:
The patent applies partial action by configuring only the necessary number of processing units and hardware unit arrays based on actual data characteristics. Rather than provisioning maximum capacity always, the system uses a configurable architecture that allocates resources proportionally to实际需求, achieving adequate throughput while minimizing power consumption and device size.
Solution Approach 2:
The patent changes the parameters of hardware architecture (number of clusters, processing units per cluster, hardware unit arrays per processing unit) to optimize the balance between throughput and power consumption. By adjusting these parameters based on streaming data characteristics, the system achieves high productivity when needed while reducing power usage when lower data rates are sufficient.
3Speed
If hardware resources are increased to reduce latency, then processing speed improves, but computational resources and memory usage increase
Solution Approach 1:
The patent uses partial action by provisioning only the necessary computational resources based on actual processing requirements. The configurable architecture allows the system to allocate processing units and hardware unit arrays proportional to the data rate and computational complexity of the streaming data, achieving low latency when needed without wasting resources during lower-demand periods.
Solution Approach 2:
The patent changes hardware parameters (number of processing units, size of hardware unit arrays) to optimize the balance between processing speed and computational resource usage. By adjusting these parameters based on streaming data characteristics, the system achieves high processing speed when data rates and computational demands are high while reducing resource consumption when demands are lower.
4Productivity
If a customized hardware architecture is generated for each data type, then processing efficiency improves, but manufacturing complexity and development time increase
Solution Approach 1:
The patent implements universality by creating a single configurable hardware architecture template that can be adapted to process various types of streaming data. Instead of designing separate custom hardware architectures for each data type or application, the template provides a universal structure where design parameters are adjusted to match specific requirements, reducing manufacturing complexity while maintaining processing efficiency.
Solution Approach 2:
The patent applies segmentation by dividing the hardware architecture into modular components (clusters, processing units, hardware unit arrays) that can be independently configured. This modular segmentation allows the template to be adapted to different data characteristics by adjusting the quantity and arrangement of modules, simplifying manufacturing compared to custom-designed architectures while achieving optimized processing efficiency.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media for generating an enhanced hardware architecture to process streaming input data are described. In one aspect, a method includes receiving data representing a hardware architecture template (195, 810). The hardware architecture template includes a set of configurable design parameters. Values for the set of design parameters are determined based on characteristics of the streaming input data (820). The determination process includes generating multiple candidate hardware architectures based on a search space for the set of configurable design parameters (840), each candidate hardware architecture including respective design parameter values, determining respective performance values associated with each candidate hardware architecture (850), selecting a hardware architecture based on the respective performance values (860), and determining the values based on parameter values associated with the selected candidate hardware architecture (870). The output data including the values is generated for instantiating the hardware architecture using the hardware architecture template.