Scalable HBM Multi-Chip Module for Legacy-to-Next-Gen Migration
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Solution Overview
Problem
Transitioning from a legacy High Bandwidth Memory (HBM) standard to a next generation standard in a chiplet-based multi-chip module (MCM) is costly and inefficient, due to uncertain scheduling and the need for significant infrastructure changes.
Innovation Solution
A multi-chip module architecture that incorporates scalable HBM memory, using a combination of legacy and next-generation HBM devices, with a daisy-chained or point-to-point configuration, allowing for efficient migration by reusing existing infrastructure and minimizing redesign costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If legacy HBM devices are used in a chiplet-based MCM, then existing infrastructure can be reused, but memory bandwidth is limited
Solution Approach 1:
The memory system is segmented into multiple HBM devices (legacy and next-generation) that are daisy-chained together. Each device handles a portion of the data channels, allowing the system to scale bandwidth by adding devices while maintaining compatibility with existing infrastructure through the modular chiplet architecture.
Solution Approach 2:
Legacy HBM devices and next-generation HBM devices are merged into a single scalable memory system. The devices are combined in a daisy-chain configuration where they collectively support the full N-channel interface, enabling both infrastructure reuse and increased bandwidth.
2Productivity
If next-generation HBM devices are deployed, then memory bandwidth increases, but infrastructure redesign costs increase
Solution Approach 1:
The MCM architecture is designed with universal compatibility to support both legacy and next-generation HBM devices. The package substrate and interconnect structure are configured to accommodate different device types, allowing the same infrastructure to serve multiple functions and device generations without requiring complete redesign.
Solution Approach 2:
The memory system is designed to be dynamically scalable, allowing the configuration of HBM devices to be adjusted based on bandwidth requirements. The system can adapt between using only legacy devices, only next-generation devices, or a hybrid configuration, providing flexibility without fixed infrastructure constraints.
3Ease of manufacture
If a hybrid configuration of legacy and next-generation HBM devices is used, then migration costs are reduced, but device configuration complexity increases
Solution Approach 1:
The package substrate serves as an intermediary that mediates between legacy and next-generation HBM devices. It provides a standardized interface and routing structure that simplifies the integration of heterogeneous devices, managing the configuration complexity while enabling cost-effective migration through the unified daisy-chain architecture.
Data Source
AI summary
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes an active silicon substrate and a memory interface circuit configured to support N memory channels. The memory interface circuit has a primary interface for coupling to a host memory interface via the N memory channels. A first HBM stack of memory die is disposed on the active silicon substrate and coupled to a secondary interface of the memory interface circuit. The first HBM stack dedicated to a first subset of the N data channels and a first data transfer rate. A second HBM stack of memory die is disposed on the active silicon substrate. The second HBM stack is positioned inline with the first HBM stack and the memory interface circuit and coupled to the secondary interface of the memory interface circuit. The second HBM stack is dedicated to a second subset of the N data channels and exhibits a second data transfer rate. The first HBM stack and the second HBM stack are configured to collectively support the N channels and exhibit an aggregate data rate that is a sum of the first data rate and the second data rate.