Scalable Inverse Discrete Cosine Transform System
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Solution Overview
Problem
Existing digital image codecs face inefficiencies in decompression time due to the need to wait for all outcomes of the first 1-D IDCT operation before performing the second, and their hardware architecture is not scalable to meet varying throughput demands, leading to increased costs and design cycle times.
Innovation Solution
A scalable IDCT system and method that uses transform control signals to decode specific columns of an output matrix in parallel, allowing multiple basic operation units to perform IDCT operations simultaneously, reducing the need for buffer memory and hardware, and enabling flexible throughput adjustments without redesigning hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the conventional row column decomposition method is used to divide 2-D IDCT operation into two 1-D IDCT operations, then the IDCT operation can be performed in a structured manner, but the system must wait for all 64 outcomes of the first 1-D IDCT operation before performing the second 1-D IDCT operation, which prolongs the decompression time
Solution Approach 1:
The patent performs preliminary actions by initiating the second 1-D IDCT operation before all outcomes of the first 1-D IDCT operation are complete. Multiple BOUs start processing partial outcomes as soon as they become available, rather than waiting for the complete set of 64 outcomes. This overlapping execution of operations reduces the total decompression time by eliminating the sequential waiting period.
2Productivity
If the conventional row column decomposition method is used, then the IDCT operation can be structured into two 1-D operations, but a buffer memory is needed to buffer the 64 intermediate values, which increases the cost of the digital image codec
Solution Approach 1:
The patent segments the IDCT processing into multiple independent Basic Operation Units (BOUs), where each BOU processes a specific portion of the data. This segmentation allows different BOUs to work on different data portions simultaneously without requiring a large centralized buffer to hold all 64 intermediate values. Each BOU only needs to buffer the specific intermediate values it requires, significantly reducing the total buffer memory capacity needed.
Solution Approach 2:
The patent implements partial action by having BOUs process only the specific portions of data they need rather than waiting for and processing all 64 outcomes. Each BOU performs its 1-D IDCT operation on partial outcomes as they become available, eliminating the need to buffer all intermediate values before processing can begin.
3Ease of manufacture
If the hardware architecture is fixed for a specific throughput, then the design is simple, but if the throughput requirement changes, the hardware must be redesigned, which wastes design resources and extends the design cycle
Solution Approach 1:
The patent creates a universal hardware architecture where a single BOU can be configured to handle different throughput requirements. By using a control signal mechanism that routes data to multiple BOUs based on throughput needs, the same basic hardware design serves multiple functions and throughput levels. This eliminates the need for complete hardware redesign when throughput requirements change.
Solution Approach 2:
The patent introduces dynamic configurability through control signals that can adjust the number of active BOUs based on throughput requirements. The system can dynamically activate or deactivate BOUs without hardware changes, allowing the same physical architecture to adapt to different performance needs. This dynamic control mechanism provides scalability while maintaining design simplicity.
Data Source
AI summary
The present invention provides an input data control method and system for a data processing system. The system comprises at least one basic operation unit (BOU) and is used for transforming one input matrix X into data in a plurality of specified columns in an output matrix Y via an inverse discrete cosine transform procedure. The method generates and outputs a transform control signal together with the input matrix to at least one of the BOUs. A new transform control signal is generated according to the received transform control signal, and outputted together with the input matrix X, to other following BOUs. The step of generating the new transform control signals is repeated until each specific column of the output matrix Y is decoded by a corresponding BOU. A basic operation procedure is then performed, and the received input matrix is decoded to obtain the data in the specified columns corresponding to the transform control signal.