Scalable I/O Architecture Reducing Latency and Power
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Solution Overview
Problem
Conventional input/output (I/O) architectures in personal computers and mobile devices are inefficient in handling data streams, requiring CPU intervention and memory access, which leads to high power consumption and latency, especially in power-sensitive mobile platforms.
Innovation Solution
The Scalable I/O (SIO) architecture introduces a novel I/O streaming domain that interacts with a load/store domain to process I/O data efficiently, eliminating the need for system memory as a FIFO buffer by using dynamic, low-latency hardware FIFO buffers and enabling peer-to-peer data transfers between I/O controllers and accelerators, thereby minimizing CPU involvement and optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional I/O architecture uses CPU and system memory for data streaming, then data processing can be performed, but power consumption increases and latency occurs
Solution Approach 1:
The patent segments the I/O data stream into multiple parallel streams and routes them through different hardware FIFO buffers and accelerators simultaneously, enabling parallel processing without CPU intervention. This segmentation allows the system to process multiple data types (audio, video, network) concurrently through dedicated hardware paths, reducing both power consumption and latency by eliminating sequential CPU-mediated memory access.
Solution Approach 2:
The patent introduces hardware FIFO buffers as intermediary components between I/O controllers and accelerators. These hardware buffers act as mediators that temporarily store data streams, allowing I/O controllers to write data asynchronously while accelerators read and process data independently. This intermediary mechanism eliminates the need for CPU-mediated data transfer and reduces latency by enabling direct hardware-to-hardware data flow.
2Productivity
If hardware FIFO buffers are added to maximize system idle times, then device driver activity frequency decreases, but latency increases
Solution Approach 1:
The patent implements dynamic buffer allocation where hardware FIFO buffers are dynamically assigned to different accelerators and data streams based on real-time system conditions and data type requirements. The buffer allocation is not static but adapts to changing workload demands, allowing the system to maximize idle times for non-critical operations while maintaining low latency for time-sensitive data streams through dynamic reconfiguration of buffer assignments.
Solution Approach 2:
The patent applies different buffer allocation strategies to different data streams and accelerators based on their specific requirements. Time-critical accelerators (e.g., audio processing) receive priority buffer allocation with smaller, faster buffers to minimize latency, while less time-sensitive accelerators (e.g., background network processing) can use larger buffers to maximize system idle times. This localized quality approach allows simultaneous optimization of both productivity and latency for different system components.
3Loss of time
If small FIFO buffers are used to reduce latency, then latency decreases, but device driver data management activity frequency increases
Solution Approach 1:
The patent enables accelerators to autonomously manage their own data buffer operations without requiring frequent device driver intervention. Each accelerator is equipped with independent control logic that allows it to read from and write to its assigned hardware FIFO buffers directly, managing its own data flow autonomously. This self-service capability reduces latency by eliminating driver-mediated access while minimizing device driver activity frequency by allowing accelerators to operate independently within their allocated buffer resources.
4Adaptability or versatility
If each I/O controller and accelerator uses unique data movement methods, then device functionality is achieved, but device complexity and software coordination requirements increase
Solution Approach 1:
The patent implements a universal hardware FIFO buffer interface standard that all I/O controllers and accelerators must adhere to. Despite each device having unique data processing capabilities and methods, they all interact with the buffer management system through a common standardized interface. This universality allows diverse devices with different functionalities to be integrated into a cohesive system without requiring complex unique coordination software for each device, reducing overall system complexity while maintaining device versatility.
Data Source
AI summary
An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.