Scalable Coherent Memory Devices for Low-Latency Sharing

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Solution Overview

Problem

Existing server systems face challenges in efficiently managing memory resources across multiple servers, leading to increased network latencies, reduced resource elasticity, and inefficiencies in data processing and storage, while also facing a shortage of feasible distributed shared memory and large address space systems, which complicates updating and increases ownership costs.

Innovation Solution

Implementing a cache-coherent protocol, such as Compute Express Link (CXL), to enable scalable and coherent memory devices by leveraging a fabric and architecture that presents a system view to workloads across racks, allowing for composable cache coherent memory and accelerator resources, and using a management computing device to route workloads based on system parameters and performance characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If servers are connected by traditional network protocols to access remote memory resources, then resource sharing is enabled, but network latencies increase and data transfer rates decrease

Engineering Contradiction:
Improveresource sharingVSAvoidnetwork latencies
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent introduces a cache-coherent interconnect fabric as an intermediary between servers and memory resources, replacing traditional network protocols. This fabric enables direct, low-latency access to memory resources across server boundaries while maintaining cache coherence, thus resolving the contradiction between resource sharing and network latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments memory resources from compute resources, allowing memory to be independently allocated and accessed by multiple servers through the cache-coherent fabric. This segmentation enables efficient resource sharing without the performance penalties of traditional networked access.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If distributed shared memory systems are implemented to increase address space, then memory capacity is improved, but system complexity and ownership costs increase

Engineering Contradiction:
Improveaddress spaceVSAvoidsystem complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The cache-coherent interconnect fabric serves multiple functions simultaneously: it provides distributed shared memory access, maintains cache coherence across servers, enables resource sharing, and supports scalable address space expansion. This multi-functionality reduces overall system complexity compared to implementing separate solutions for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If more memory resources are allocated to servers, then processing capacity is improved, but power consumption and bandwidth requirements increase

Engineering Contradiction:
Improveprocessing capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges memory resources from multiple servers into a shared pool accessible through the cache-coherent fabric. This consolidation reduces total power consumption by eliminating redundant memory controllers and interfaces, while still providing high processing capacity through efficient shared access.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12436885B2Systems and methods for scalable and coherent memory devices
Publication Date: 2025.10.07 SAMSUNG ELECTRONICS CO LTD
  • US12436885B2 patent drawing
  • US12436885B2 patent drawing
  • US12436885B2 patent drawing

AI summary

Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.