Scalable Neural Circuit with Time-Multiplexed Synapse and STDP
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Solution Overview
Problem
Existing neural networks lack scalable and programmable neural circuits with spike timing dependent plasticity (STDP) and interconnect fabric, limiting their ability to implement dynamic spiking neural circuits and synapses effectively.
Innovation Solution
A reconfigurable neural network architecture with time-multiplexed synapse and STDP circuits, integrated with memristor memories and CMOS circuitry, allowing for scalable implementation of spiking neurons and synapses with programmable connections and interconnects, enabling flexible neural network topologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If neurons are located only in the periphery of a synaptic array, then the circuit layout is simplified, but the number of neurons scales only linearly with the horizontal or vertical dimension
Solution Approach 1:
The patent transitions from linear scaling (peripheral neurons only) to two-dimensional scaling by placing neurons throughout the array area. This allows the number of neurons to scale with the area of the array rather than just the perimeter, achieving quadratic scaling improvement while maintaining organized interconnect structures.
Solution Approach 2:
The patent divides the synaptic array into multiple segments or blocks, each with its own local interconnect structure. This segmentation allows neurons to be distributed throughout the array while maintaining manageable interconnect complexity through modular organization.
2Adaptability or versatility
If connections are made programmable with interconnect fabric, then network topology flexibility is improved, but circuit complexity and interconnection requirements increase
Solution Approach 1:
The patent employs time-division multiplexing where interconnect resources are allocated in periodic time slots to different neuron pairs. This allows a reduced set of physical interconnects to support programmable network topologies by sequentially establishing different connection patterns over time, reducing simultaneous interconnect requirements.
Solution Approach 2:
The patent designs universal interconnect structures that can be configured to serve multiple neuron pairs through programmable switching. Each interconnect resource can be dynamically assigned to different neuron connections based on the required network topology, reducing the total number of dedicated interconnects needed.
Data Source
AI summary
A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.