Scalable Packet Processor Context Generation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing packet-based processing systems face inefficiencies and increased hardware complexity due to the need to handle multiple communication protocols, leading to exponential growth in redundant hardware and limited scalability.

Innovation Solution

A scalable packet processor with packet match logic and context generation logic that uses modular arithmetic to generate context identifiers, allowing efficient distribution of packets across multiple contexts without linear scaling of hardware complexity, supporting different protocols and header sizes through configurable registers and a lookup table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional nodes are added to convert packet traffic between protocols, then cross-protocol communication capability is improved, but hardware complexity and system size grow exponentially

Engineering Contradiction:
Improvecross-protocol communication capabilityVSAvoidhardware complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The packet processor is designed with a universal packet format that can handle multiple communication protocols (Ethernet, InfiniBand, PCIe, CXL) through a single unified processing path. The processor uses configurable fields in the packet header to identify and route different protocol types without requiring separate conversion nodes, enabling one device to perform multiple protocol handling functions simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a standardized intermediate packet format that serves as a mediator between different communication protocols. Incoming packets from various protocols are converted into this universal intermediate format for processing, then converted to the appropriate destination protocol format. This intermediary format eliminates the need for direct protocol conversion nodes between each protocol pair.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If packets of multiple protocols are separated onto different data paths, then processing complexity per path is reduced, but hardware redundancy increases exponentially

Engineering Contradiction:
Improveprocessing simplicityVSAvoidhardware redundancy
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges multiple protocol processing paths into a single unified data path. Instead of maintaining separate hardware paths for each protocol, the system uses one processing path that handles all protocols through configurable packet format recognition and routing based on header field analysis. This consolidation eliminates redundant hardware while maintaining processing simplicity through standardized handling.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The packet processing is segmented into distinct functional stages: packet reception, format identification through header field comparison, context determination, and routed distribution. This segmentation allows a single unified path to handle multiple protocols efficiently by breaking down the processing into manageable, protocol-agnostic steps that can be configured for different protocol types.

Inventive Principle:
Principle #1Segmentation

3Productivity

If processing and communication capabilities are increased, then system performance is improved, but hardware cost and latency increase due to exponential growth in redundant hardware

Engineering Contradiction:
Improveprocessing capabilityVSAvoidhardware cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The packet processor incorporates dynamic configurability through programmable fields that can be adjusted to handle different protocol types and processing requirements. The system can dynamically adapt its processing behavior based on the incoming packet format identification, allowing a single hardware instance to provide multiple processing capabilities without requiring redundant dedicated hardware for each capability level.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240244001A1Scalable Packet Processing
Publication Date: 2024.07.18 MARVELL ASIA PTE LTD
  • US20240244001A1 patent drawing
  • US20240244001A1 patent drawing
  • US20240244001A1 patent drawing

AI summary

The present disclosure describes apparatuses and methods for scalable packet processing. In some aspects, match logic of a scalable packet processor extracts and compares bits from a packet header to determine if the packet matches a context. The match logic may also determine a context index value based on other bits extracted from the header. In response to the match and based on a virtual function associated with the packet, context generation logic of the packet processor obtains a base context value and a context range value from a lookup table. The context generation logic then determines a context identifier for the packet based on the context index value, base context value, and context range value through modular arithmetic. Accordingly, the packet processor can generate context identifiers for packet distribution across contexts without maintaining a table of every context, enabling efficient scaling of the packet processor with less silicon area.