Scalable Parity Code for Variable-Length Data Packets

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional error control codes, such as CRC32, are inflexible and not scalable, leading to inefficient data packet transmission as they consume too many bits for small packets and limit data length, failing to adapt to varying payload sizes.

Innovation Solution

A scalable error control code (ECC) protocol that dynamically adjusts the number of parity bits based on the data packet size, using a table to generate parity bits that match the number of data bits, thereby optimizing bit usage and reducing overhead without changing the ECC processing method.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error control codes (e.g., CRC32) are used, then error detection capability is provided, but the number of parity bits is fixed and excessive for small packets, increasing protocol overhead

Engineering Contradiction:
Improveerror detection capabilityVSAvoidprotocol overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic scalability by allowing the number of parity bits to vary based on packet size. The ECC protocol supports configurable parity bit lengths (e.g., 8, 16, 32 bits) that can be selected according to the actual data payload size, transforming the fixed static structure into a dynamic adaptive one that optimizes overhead for different packet scenarios

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of parity bit length from a fixed value to a variable that adapts to packet size. By modifying this key parameter based on data length, the system achieves optimal balance between error detection reliability and protocol efficiency, avoiding the waste of excessive parity bits on small packets while maintaining sufficient protection for larger packets

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If fixed-length parity bits are used, then error control is simplified, but data packet length is limited and scalability is reduced

Engineering Contradiction:
ImproveECC processing simplicityVSAvoidpacket length flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the ECC processing into multiple configurable stages or modes, where different parity bit lengths can be selected based on packet requirements. This segmentation allows the system to maintain simple processing for small packets while providing extended capacity for larger packets, achieving both simplicity and scalability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ECC protocol is designed with multi-functionality to handle various packet sizes and types. By incorporating configurable parity bit lengths and supporting different ECC modes within a single protocol framework, the system achieves universal applicability across diverse communication scenarios without requiring multiple specialized protocols

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If more parity bits are used, then error detection reliability improves, but energy consumption increases

Engineering Contradiction:
Improveerror detection reliabilityVSAvoidtransmission energy
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by using only the necessary number of parity bits required for each specific packet size rather than always using the maximum number. This partial approach ensures sufficient error detection reliability for each packet while avoiding the excessive energy consumption that would result from using fixed maximum-length parity bits for all packets

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10838813B2Progressive length error control code
Publication Date: 2020.11.17 MICRON TECHNOLOGY INC
  • US10838813B2 patent drawing
  • US10838813B2 patent drawing
  • US10838813B2 patent drawing

AI summary

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.