Scalable Partial Vectorization via Latency-Based Expression Tree Selection
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Solution Overview
Problem
Traditional partial vectorization approaches face scalability issues, particularly when dealing with basic blocks containing hundreds of instructions, as they either suffer from high compile times or produce non-optimal vectorized code, failing to maximize instruction vectorization and minimize packing and unpacking costs.
Innovation Solution
A method that computes latencies of expression trees, selects isomorphic and independent trees, and generates vectorization code based on these, reducing compile time and optimizing vectorization by grouping expressions with the same latency and reordering statements to simplify vectorization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dynamic programming is used for partial vectorization, then the number of packing and unpacking instructions is minimized and the longest expressions are vectorized, but compile time becomes extremely high and it does not scale when there are hundreds of high level statements
Solution Approach 1:
The patent segments the basic block analysis into multiple passes: first identifying all isomorphic expressions, then selecting a subset for vectorization based on criteria such as expression length and independence. This segmentation allows the compiler to avoid the exhaustive comparison of all expressions required by dynamic programming, thereby reducing compile time while still achieving high-quality vectorization of the most important expressions.
Solution Approach 2:
Instead of vectorizing all isomorphic expressions as dynamic programming would do, the patent applies partial vectorization by selecting only a subset of expressions for vectorization. This partial action reduces the compile time and the number of generated vector instructions while still capturing the most beneficial vectorization opportunities, thus resolving the contradiction between optimization quality and compile time.
2Productivity
If greedy algorithms are used for partial vectorization, then compile time is reasonable and it scales with hundreds of high level statements, but the solution is not optimal and does not maximize the number of instructions vectorized
Solution Approach 1:
The patent incorporates feedback mechanisms by analyzing the characteristics of isomorphic expressions and using this information to guide the selection process. The compiler evaluates expression properties such as length, independence, and vectorization potential, then uses this feedback to prioritize which expressions to vectorize. This feedback-driven approach ensures that the most beneficial expressions are selected, improving vectorization quality while maintaining reasonable compile time.
Solution Approach 2:
The patent changes the selection criteria parameters from simple greedy heuristics to more sophisticated multi-criteria evaluation. By considering multiple parameters simultaneously (expression length, independence from other vectorized expressions, vectorization benefit), the patent achieves better optimization quality while maintaining the scalability and reasonable compile time of greedy algorithms.
3Manufacturing precision
If all independent and isomorphic expressions are compared with each other to ensure optimal vectorization, then the longest expressions are vectorized, but the compile time is extremely high when compiling basic blocks containing hundreds of statements
Solution Approach 1:
The patent segments the set of all isomorphic expressions into groups based on their vectorization potential and characteristics. By dividing the analysis into manageable segments and processing them in priority order, the patent avoids the need to compare all expressions exhaustively, thereby reducing analysis complexity while still achieving optimal vectorization of the most important expressions.
Solution Approach 2:
The patent performs preliminary analysis to identify and categorize all isomorphic expressions before the actual vectorization selection. This preliminary action includes computing expression properties, identifying independence relationships, and ranking expressions by vectorization potential. By performing this preliminary work upfront, the patent reduces the complexity of the subsequent selection process while ensuring optimality.
Data Source
AI summary
A system, method and computer program product to compute latencies of a plurality of expression trees in a basic block and to select a first and a second expression tree from the plurality of expression trees based on the computed latencies. The first expression tree is isomorphic to the second expression tree and the first and second expression trees are selected in order of largest to smallest latency. This selection ensures that the largest isomorphic expression trees are vectorized first. By vectorizing the largest isomorphic expression trees first, a basic block containing hundreds of statements can be vectorized without significant compile time. Moreover, vectorization of the largest isomorphic expression trees results in a significant improvement in system performance on SIMD processors.