Scalable Phased Array Package with Embedded Transmission Lines

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Solution Overview

Problem

Conventional techniques for scaling phased arrays result in complex assembly processes, thermal mismatch issues, non-symmetric frequency combining, large printed circuit board sizes, and inefficient use of wafers due to the need for external components and multiple interfaces.

Innovation Solution

A scalable phased array design incorporating a die with multiple integrated circuits and embedded transmission lines within an antenna-in-package substrate, which simplifies assembly and reduces the number of interfaces by using a ball grid array terminal and combiner to couple flip chip pads to BGA terminals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional daisy chain combining or stitching techniques are used to scale phased arrays, then additional antenna elements can be supported through multiple integrated circuits, but the number of assembly steps increases undesirably

Engineering Contradiction:

Improvescaling capabilityVSAvoidassembly steps

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple integrated circuits onto a single package substrate, integrating what would traditionally be separate modules into one unified structure. This merging eliminates the need for multiple assembly steps while maintaining the ability to support additional antenna elements through the integrated circuit architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The package substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection through embedded transmission lines, thermal management pathways, and signal combining capabilities. This multi-functionality reduces the need for separate components and assembly steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple discrete integrated circuits are used to scale phased arrays, then operational capacity can be enhanced, but mismatched coefficients of thermal expansion between chips, packages, and printed circuit board occur

Engineering Contradiction:

Improveoperational capacityVSAvoidthermal mismatch

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

By integrating multiple integrated circuits onto a single package substrate rather than using discrete chips, the patent reduces the number of material interfaces. The unified structure minimizes thermal expansion mismatches that would occur between multiple different chip materials, package materials, and PCB materials.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If conventional stitching techniques are used to scale phased arrays, then additional antenna elements can be supported, but non-symmetric combining in amplitude and timing occurs due to loss and delay accumulation

Engineering Contradiction:

Improvescaling capabilityVSAvoidamplitude and timing symmetry

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements symmetric routing paths for signal transmission within the package substrate, ensuring that signals traveling to different antenna elements experience equalized delay and loss characteristics. This local optimization of signal paths maintains amplitude and timing symmetry across scaled array elements.

Inventive Principle:

Principle #3Local quality

4Ease of manufacture

If external components are used to support the array in conventional techniques, then the phased array can be assembled, but the printed circuit board size increases

Engineering Contradiction:

Improveassembly capabilityVSAvoidprinted circuit board size

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent integrates transmission lines, combiners, and other signal processing functions directly into the package substrate, eliminating the need for external components on the PCB. This integration significantly reduces the required PCB area while maintaining full assembly capability.

Inventive Principle:

Principle #5Merging (Combining)

5Adaptability or versatility

If conventional scaling techniques are used with multiple integrated circuits, then phased array capacity can be increased, but wafer utilization efficiency decreases

Engineering Contradiction:

Improvearray capacityVSAvoidwafer utilization efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

By consolidating multiple integrated circuits into a single package, the patent improves wafer utilization efficiency. Instead of requiring separate wafers for each circuit, the integrated approach allows more circuits to be produced from fewer wafers, thereby improving productivity and reducing waste.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10784563B2Scalable phased array package

Publication Date: 2020.09.22 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Techniques regarding a scalable phased array are provided. For example, various embodiments described herein can comprise a plurality of integrated circuits having respective flip chip pads, and an antenna-in-package substrate having a ball grid array terminal and a plurality of transmission lines. The plurality of transmission lines can be embedded within the antenna-in-package substrate and can operatively couple the respective flip chip pads to the ball grid array terminal. In one or more embodiments, a die can comprise the plurality of integrated circuits. Further, in one or more embodiments a combiner can also be embedded in the antenna-in-package substrate. The combiner can join the plurality of transmission lines.