Scalable Processor for Multi-Value Logic Verification
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Solution Overview
Problem
Conventional logic simulators are inadequate for efficiently evaluating large and complex electronic systems, requiring excessive time and resources to determine if designs meet desired functionality and performance, especially with the introduction of new language constructs like Verilog 2000.
Innovation Solution
A scalable simulation system with a processor capable of efficiently evaluating circuit signal values using parameterized instructions, supporting up to 8 operands and encoding digital circuit signal values beyond two states, allowing for rapid verification of complex circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional logic simulators are used to evaluate large and complex electronic systems, then design verification can be performed, but the evaluation time and resource consumption become excessive
Solution Approach 1:
The patent creates a simplified behavioral model (copy) of the complex electronic design that captures essential verification characteristics without replicating all detailed circuit behavior. This behavioral model executes faster while maintaining sufficient accuracy for design verification, resolving the contradiction between verification accuracy and evaluation time.
Solution Approach 2:
The patent divides the complex design evaluation into segmented phases: detailed circuit-level simulation for critical paths and behavioral-level simulation for overall system verification. This segmentation allows time-consuming detailed simulation to be limited to only necessary portions while using faster behavioral simulation for the remainder, reducing total evaluation time while maintaining verification accuracy.
2Reliability
If conventional logic simulators are used for complex circuit verification, then functionality can be assessed, but the system lacks capacity to handle large-scale designs efficiently
Solution Approach 1:
The patent introduces a hierarchical dimension to verification by operating at multiple levels: detailed circuit level for reliability-critical components and behavioral abstraction level for system-wide productivity. This dimensional approach allows simultaneous maintenance of verification reliability for critical functions and high productivity for overall system validation.
Solution Approach 2:
The patent dynamically changes simulation parameters such as time granularity, signal detail level, and model fidelity based on the verification phase and design region. During early exploration phases, coarse-grained behavioral parameters enable high throughput; during final verification, fine-grained circuit parameters ensure reliability. This parameter adaptation resolves the contradiction between verification reliability and productivity.
3Measurement precision
If detailed circuit simulation is performed to ensure accurate verification, then design errors can be detected, but the complexity and resource requirements increase significantly
Solution Approach 1:
The patent implements dynamic adjustment of simulation detail level based on verification needs. The system automatically transitions between detailed circuit simulation and behavioral simulation modes, adjusting model complexity in real-time. This dynamic approach maintains high error detection accuracy when needed while reducing simulation system complexity during phases requiring less detail, resolving the contradiction between precision and complexity.
Data Source
AI summary
A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.