Scalable Processor Task Distribution via Repetition Indexing
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Solution Overview
Problem
Traditional digital signal processors (DSPs) face performance delays and reduced efficiency due to repeated instruction sequences, which lead to frequent access of the instruction memory, thereby reducing processing power and increasing latency.
Innovation Solution
The method involves identifying and outsourcing high-repetition sub-sequences to external processing units, while executing low-repetition sequences in the core processor, allowing for flexible resource allocation and reduced instruction memory access, thereby enhancing performance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If repeated instruction sequences are executed by a single processor core, then the processor can maintain a simple architecture, but processing efficiency deteriorates due to frequent instruction memory access
Solution Approach 1:
The processor is divided into a core processor and multiple external processing units. The core processor handles control functions and low-repetition sequences, while external processing units handle high-repetition sub-sequences. This segmentation allows the system to maintain simple core architecture while improving overall processing efficiency through parallel execution of repeated sequences in external units.
2Loss of time
If high-repetition sub-sequences are executed in the core processor, then instruction memory access is reduced, but processing resources are underutilized
Solution Approach 1:
The system automatically identifies repeated sub-sequences and dynamically allocates them to external processing units based on repetition rate. The core processor serves itself by handling only control instructions and low-repetition sequences, while external units self-service by executing high-repetition sequences independently, reducing instruction memory access and improving resource utilization.
3Productivity
If external processing units are added to handle repeated sequences, then processing efficiency improves, but device complexity increases
Solution Approach 1:
External processing units are designed as universal components that can be dynamically allocated to handle different high-repetition sub-sequences based on the application requirements. The same external processing units can be reconfigured to handle different repeated sequences, providing multi-functionality without increasing the number of dedicated hardware components for each sequence.
4Power
If instruction memory access is frequent, then processing power is reduced, but power consumption increases
Solution Approach 1:
High-repetition sub-sequences are extracted from the core processor's execution flow and offloaded to external processing units. This extraction reduces the frequency of instruction memory access in the core processor, thereby reducing power consumption while maintaining processing power for control functions and non-repeated sequences.
Data Source
AI summary
A processing method and apparatus for processing an information is based on a sequence of instructions, where a repeated sub-sequence is detected in the sequence of instructions and an allocation between a processing resource and the repeated sub-sequence is determined based on an index information indicating the repetition frequency of the repeated sub-sequence. Thus, a combination of a scalable signal processor with automatic task distribution is provided, where the number of memory accesses can be reduced, as the repeated sub-sequence can be allocated to external processing units, which are correspondingly programmed or which use their embedded memory.