Scalable Radar-on-Chip Array Architecture for Channel Expansion
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Solution Overview
Problem
The integration of multiple transmitter and receiver channels on a single semiconductor radar chip increases the size, cost, and complexity of the die, limiting its flexibility and making it less suitable for less demanding applications.
Innovation Solution
A scalable radar on chip (SROC) architecture that includes a fractional-N PLL synthesizer, digital ramp generator, transmitter section with multiple transmitter chains, and receiver section with multiple receiver chains based on homodyne architecture, allowing for flexible configuration and reduced engineering and manufacturing costs by enabling the use of multiple SROCs in an array configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transmitter and receiver channels are integrated on a single semiconductor radar chip, then the radar performance and channel capacity are improved, but the die size, manufacturing cost, and system complexity increase
Solution Approach 1:
The radar system is segmented into multiple independent SROC units, each containing a complete set of transmitter and receiver chains. These modular units can be independently manufactured and then combined in array configurations to achieve the desired total channel capacity, distributing the complexity across multiple manageable components rather than one large integrated chip
Solution Approach 2:
Multiple SROC units are nested or combined in array configurations where each unit contains a complete functional radar system. This nesting approach allows smaller functional units to be composed into larger systems, achieving high channel capacity while maintaining manageable complexity at each level
2Productivity
If multiple transmitter and receiver channels are integrated on a single semiconductor radar chip, then the radar performance is improved, but the manufacturing cost increases
Solution Approach 1:
The system is divided into multiple SROC units that can be manufactured using standard semiconductor fabrication processes at reasonable volumes. By segmenting the total channel capacity requirement into multiple units, each unit can be manufactured more cost-effectively than a single large-scale integrated chip, and the modular approach enables better utilization of fabrication capacity
Solution Approach 2:
Multiple identical SROC units are created as copies of a standardized design. This copying approach allows for economies of scale in manufacturing, as each unit follows the same fabrication process and design specifications, reducing per-unit costs compared to custom high-volume integration on a single chip
3Adaptability or versatility
If a single radar chip contains many transmitter or receiver chains, then high-end applications are supported, but flexibility for less demanding applications is reduced
Solution Approach 1:
The radar system is segmented into modular SROC units that can be configured in different array sizes and configurations. This segmentation enables flexible system design where the number of transmitter and receiver chains can be adjusted by changing the array configuration rather than being fixed in a single large integrated chip, allowing adaptation to various application requirements from low-end to high-end
Solution Approach 2:
The system architecture is made dynamic and reconfigurable, allowing the SROC units to be arranged in different array configurations depending on the application requirements. This dynamic configurability enables the same basic building blocks to serve multiple application scenarios, from simple detection to complex imaging and surveillance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SROC architecture provides a powerful system with scalable transmitter and receiver channels, reducing costs and increasing flexibility, enabling effective use in both high-end and less demanding applications by allowing the number of channels to be adjusted based on the number of SROCs used.
Implementation Method 1
The SROC architecture mainly comprises four parts—a fractional-N PLL synthesizer
Implementation Method 2
a Tx (Transmitter) section composed of a frequency multiplier and Y number of transmitter chains
Implementation Method 3
an Rx (Receiver) section composed of Z number of receiver chains based on a homodyne architecture
Data Source
AI summary
A multiple scalable radar on chip (SROC) based system in a multi-array configuration; may include: a first SROC; and a second SROC. The first SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The second SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The ramp generator of the first SROC may be configured to drive the fractional-N PLL synthesizer of the second SROC. The fractional-N PLL synthesizer of the second SROC may be configured to produce radio frequency (RF) ramp signals to drive both the first and second SROCs. ‘Y’ and ‘Z’ may represent positive integers.