Scalable Scribe Regions for Dynamic Function Exchange

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Solution Overview

Problem

Dynamic function exchange in programmable integrated circuits faces challenges with bleed-over routes, which reduce available routing resources and cause congestion hotspots, leading to circuit timing and routing failures, especially in user circuit designs.

Innovation Solution

The implementation of a scalable scribe region with multiple contours that restricts component placement and reduces routing congestion by allowing bleed-over routes, facilitating a smaller platform circuitry footprint and minimizing the risk of implementation failures through iterative sizing and design metrics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If platform circuitry is implemented with minimal footprint to maximize user circuit design space, then area available for user circuit design is improved, but routing congestion and timing failures worsen due to bleed-over routes

Engineering Contradiction:

Improvearea available for user circuit designVSAvoidrouting reliability

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent segments the IC into distinct floorplan areas with clearly defined boundaries between platform circuitry and user circuit design regions. Scribe regions are introduced as buffer zones that segment the routing paths, preventing bleed-over routes from causing congestion in user design areas while maintaining minimal platform footprint.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces scribe regions as intermediary zones between platform circuitry and user circuit designs. These scribe regions act as mediators that absorb and manage bleed-over routes, preventing them from causing routing congestion and timing failures in user design areas while allowing the platform circuitry to maintain a minimal footprint.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If scribe region size is increased to prevent routing congestion, then routing reliability is improved, but area available for user circuit design worsens

Engineering Contradiction:

Improverouting reliabilityVSAvoidarea available for user circuit design

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The patent implements dynamic scribe region sizing where the extent of scribe regions is not fixed but adapts based on the specific platform circuitry design and user circuit design requirements. The EDA system can selectively apply scribe regions of different sizes in different areas, optimizing the balance between routing reliability and user design space utilization.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies scribe regions with locally optimized sizes and shapes tailored to specific areas of the IC. Rather than using a uniform scribe region throughout, the EDA system determines appropriate scribe region characteristics for each local area based on platform circuitry layout, routing requirements, and user design constraints, maximizing area efficiency while maintaining routing reliability.

Inventive Principle:

Principle #3Local quality

3Adaptability or versatility

If multiple contours are provided for scribe regions to enable iterative sizing, then adaptability is improved, but device complexity worsens

Engineering Contradiction:

Improveadaptability of scribe region sizingVSAvoidcomplexity of EDA system

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements multiple contours for scribe regions, providing more sizing options than strictly necessary. This partial excess of design options enables iterative refinement and adaptation to various platform circuitry configurations and user design requirements, with the EDA system selecting the appropriate level of detail based on specific design needs.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent creates a universal scribe region framework with multiple contours that can be applied across different platform circuitry designs and user circuit designs. The same multi-contour scribe region mechanism serves multiple functions: defining initial boundaries, providing iterative sizing options, managing bleed-over routes, and adapting to various design scenarios, reducing the need for separate mechanisms for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230098098A1Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange

Publication Date: 2023.03.30 XILINX INC

AI summary

Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.