Scalable Sockets for Network Packet Processing

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Solution Overview

Problem

In high data rate network architectures, conventional methods for distributing packet processing across multiple CPU cores face inefficiencies due to lock contention and cache bouncing, leading to bottlenecks and reduced performance.

Innovation Solution

The solution involves replicating state associated with listening and unconnected sockets for each RSS processor, ensuring that each processor handles its own state, thereby minimizing cache bouncing and optimizing processing by aligning APP processors with RSS processors for efficient packet handling and state management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If packet processing is distributed across multiple CPU cores using RSS, then processing throughput is improved, but lock contention increases causing performance degradation

Engineering Contradiction:
Improvepacket processing throughputVSAvoidlock wait time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the shared socket state into per-CPU instances, where each CPU core has its own copy of socket state (such as receive queues, connection tracking, and buffer pointers). This segmentation eliminates the need for locks when CPUs access their local state instances, as each CPU operates independently on its own data copy. The segmentation transforms the monolithic shared state into distributed independent state instances that can be accessed without synchronization overhead.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If socket state is shared across multiple CPU cores, then memory utilization is optimized, but cache bouncing occurs reducing processing efficiency

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoidprocessing efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies local quality by making socket state locally specific to each CPU core. Instead of having uniform shared state accessible by all CPUs, each CPU gets its own instance of socket state with local ownership. This localizes the state to the CPU that needs it most, ensuring that frequently accessed state remains in the local CPU cache and avoids bouncing between caches of different CPUs. The local quality principle transforms shared global state into localized per-CPU state.

Inventive Principle:
Principle #3Local quality

3Reliability

If locks are used to protect shared socket state, then data consistency is maintained, but processor blocking occurs reducing system responsiveness

Engineering Contradiction:
Improvedata consistencyVSAvoidprocessor responsiveness
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent extracts the locking mechanism from the socket state management system by eliminating shared state entirely. Instead of protecting shared state with locks, each CPU operates on its own independent state instance. This extraction removes the blocking lock mechanism from the system, allowing CPUs to access and modify their local state instances without any synchronization barriers. The taking out principle removes the harmful locking overhead while preserving data consistency through isolation.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP2618257B1Scalable sockets
Publication Date: 2018.08.15 SOLARFLARE COMMUNICATIONS INC
  • EP2618257B1 patent drawingFigure 1~2

AI summary

A data processing system supporting a network interface device for connection to a network, the data processing system comprising: a plurality of sets of one or more data processing cores; and an operating system arranged to support at least one unconnected socket operable to accept data received from the network, the data belonging to one of a plurality of data flows; wherein the unconnected socket is configured to provide an instance of at least some of the state associated with the data flows per said set of data processing cores.