2D Scalable Storage Format for NAND Flash Reliability
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Solution Overview
Problem
Existing data storage systems, such as SSDs and HDDs, face challenges in maintaining performance and longevity due to high error rates in NAND flash memories, where fixed error correction codes often fail to recover outlier regions with high bit error rates, leading to reduced reliability and endurance.
Innovation Solution
A two-dimensional scalable versatile storage format is implemented, where a processor configures and modifies storage regions by combining horizontal and vertical dimension scaling based on performance capabilities, dynamically adjusting the storage format to reduce bit error rates and improve reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed error correction codes are applied to NAND flash memories, then data integrity is improved, but performance and longevity are reduced
Solution Approach 1:
The patent implements dynamic storage formats that can be modified based on performance capabilities and error rates. The storage format is not fixed but can be adjusted in real-time to balance between error correction strength and performance requirements, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent applies different storage formats to different storage regions based on their specific error rates and performance capabilities. Instead of using a uniform error correction approach across all regions, the system tailors the storage format locally to each region's characteristics, optimizing both reliability and performance for each area.
2Reliability
If strong error correction is applied to all storage regions, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The system applies different levels of error correction to different storage regions based on their specific needs. Regions with higher error rates receive stronger error correction, while regions with lower error rates use lighter correction schemes, reducing overall device complexity while maintaining reliability where needed.
Solution Approach 2:
The patent changes the parameters of the storage format dynamically based on performance capabilities and error rates. By adjusting parameters such as code rate, block size, and format structure, the system optimizes the balance between reliability and complexity without requiring overly complex fixed error correction mechanisms.
3Ease of operation
If storage format is fixed, then ease of operation is maintained, but adaptability to different error rates is reduced
Solution Approach 1:
The storage format transitions from a fixed structure to a dynamic one that can be modified based on performance capabilities and error rates. The system automatically adjusts the storage format without requiring manual intervention, maintaining ease of operation while gaining adaptability to different storage region characteristics.
Data Source
AI summary
The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.