Scalable Stream Synaptic Supercomputer Parallel Processing
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Solution Overview
Problem
Current neuromorphic systems, such as the IBM TrueNorth chip, face challenges in achieving high throughput due to sequential processing of neurons, which leads to increased energy consumption and wiring complexity, especially when spike packets need to traverse multiple hops across 2D grids, resulting in delayed information delivery and inefficient use of resources.
Innovation Solution
The implementation of a scalable stream synaptic supercomputer that determines the firing state of neurons in parallel and delivers this information across interconnected neurosynaptic cores using a permutation network, allowing for parallel communication and reducing the need for serial messaging in 2D mesh router architectures, thereby optimizing energy consumption and area while achieving high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential processing of neurons is used in 2D grid architecture, then wiring complexity is reduced, but throughput is limited and energy consumption increases
Solution Approach 1:
The system segments the neural network into multiple independent neurosynaptic cores, each capable of parallel processing. This segmentation allows simultaneous computation across multiple cores, dramatically increasing throughput while maintaining efficient local wiring within each core.
Solution Approach 2:
The patent transitions from sequential processing within a single 2D grid to a three-dimensional architecture where multiple 2D grids (cores) are stacked and interconnected. This dimensional expansion enables parallel processing across cores while maintaining the efficient 2D wiring topology within each layer.
2Speed
If sequential processing of neurons is used, then device complexity is reduced, but information delivery is delayed
Solution Approach 1:
The neural network is divided into multiple neurosynaptic cores that process information simultaneously. Each core maintains a simplified internal structure for low complexity, while the segmentation across cores enables parallel information delivery, dramatically increasing speed without requiring complex inter-neuron wiring.
Solution Approach 2:
Multiple simple 2D grid cores are merged into a unified parallel processing system through the inter-core network. This merging maintains the simplicity of individual cores while achieving high-speed information delivery through simultaneous operation of multiple cores.
3Productivity
If parallel processing of neurons is implemented, then throughput increases, but wiring complexity increases
Solution Approach 1:
The system segments the large-scale parallel processing task into multiple independent neurosynaptic cores. Each core implements parallel processing locally with simple wiring, while the segmentation prevents the need for complex global wiring that would connect every neuron to every other neuron across the entire system.
Solution Approach 2:
The patent resolves wiring complexity by moving from a single large 2D grid to a 3D architecture of multiple stacked 2D grids. This dimensional change allows parallel processing across cores through vertical interconnections, maintaining efficient 2D wiring within each layer while enabling system-level parallelism.
Data Source
AI summary
A scalable stream synaptic supercomputer for extreme throughput neural networks is provided. The firing state of a plurality of neurons of a first neurosynaptic core is determined substantially in parallel. The firing state of the plurality of neurons is delivered to at least one additional neurosynaptic core substantially in parallel.