Scalable VLSI Architecture for Compressive Sensing Signal Reconstruction
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Solution Overview
Problem
Compressive sensing techniques face challenges in real-time processing efficiency due to high computational complexity, particularly on mobile platforms, limiting their application in data acquisition systems such as biomedical devices.
Innovation Solution
A scalable VLSI architecture is developed, incorporating vector and scalar computation cores, data-path memories, and a global control unit to perform compressive sensing hardware reconstruction, utilizing incremental Cholesky factorization and dynamic configuration to reduce computational complexity and enhance energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital reconstruction using greedy heuristics or convex relaxations is used, then signal reconstruction accuracy is improved, but computational complexity increases by 1-2 orders of magnitude
Solution Approach 1:
The patent replaces traditional software-based greedy heuristics and convex relaxation methods with a dedicated hardware VLSI architecture. This substitution of computational mechanics enables parallel processing of the three main OMP tasks (atom searching, least squares solving, and estimation update) simultaneously, reducing computational complexity by 1-2 orders of magnitude while maintaining reconstruction accuracy
Solution Approach 2:
The VLSI architecture divides the reconstruction process into three independent functional modules: atom searching unit, least squares solving unit, and estimation update unit. Each module processes its specific task in parallel, avoiding the sequential execution bottleneck of software implementations and reducing overall computational complexity
2Adaptability or versatility
If traditional software-based reconstruction methods are used, then flexibility in handling different signal types is improved, but processing speed decreases significantly
Solution Approach 1:
The VLSI architecture incorporates dynamic configuration capabilities that allow the hardware to be reconfigured for different signal types and reconstruction parameters. The architecture can adaptively adjust processing parameters while maintaining hardware acceleration, achieving both speed and flexibility
3Speed
If computational power is increased to achieve real-time processing, then processing speed is improved, but energy consumption increases
Solution Approach 1:
The VLSI architecture is designed to perform all reconstruction computations locally at the sensing node without requiring external computational resources. This self-contained hardware implementation eliminates the energy cost of data transmission to remote processors and enables real-time processing with reduced overall system energy consumption
Data Source
AI summary
Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.