Scale-Out Data Storage Controller Architecture
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Solution Overview
Problem
Existing data storage devices with non-volatile memory face performance degradation due to increasing mapping table sizes as storage capacity is expanded, leading to slower data processing speeds.
Innovation Solution
A data storage device with a scale-out structure that includes a controller connected to multiple clusters, each with a scale-out controller and buffer, allowing for efficient expansion of storage capacity without compromising processing speed by distributing data processing operations across multiple sub-channels and non-volatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more non-volatile memory devices are added to expand storage capacity, then data storage capacity is improved, but mapping table size increases and data processing speed deteriorates
Solution Approach 1:
The patent divides the storage system into multiple independent clusters, each with its own controller and buffer. Each cluster manages a subset of non-volatile memory devices and maintains its own mapping table, thereby segmenting the previously monolithic mapping table into smaller, manageable portions that do not collectively slow down data processing operations
Solution Approach 2:
The patent introduces a hierarchical control structure with a main controller coordinating multiple cluster controllers. This adds a dimensional layer to the control architecture, allowing parallel management of multiple memory subsets simultaneously, thus maintaining processing speed while expanding capacity across multiple dimensions
Data Source
AI summary
A data storage device includes a controller connected via a plurality of channels to a plurality of clusters, wherein each cluster comprises a scale-out device including a scale-out controller and a buffer. The scale-out controller is connected to a plurality of sub-channels, each one of the plurality of sub-channels connecting a group of non-volatile memory (NVM) devices, such that the scale-out controller controls execution of data processing operations directed to any one of the NVM devices and the buffer.