Scale-Out Storage Controller Command Protocol for Flash Durability
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Solution Overview
Problem
Existing data storage devices face performance degradation due to the variability in durability and performance of individual flash memory chips, leading to reduced overall durability and processing speed, especially in scale-out storage systems where multiple chips are used.
Innovation Solution
A data storage device architecture that includes a scale-out storage system with a controller capable of generating and managing commands using a new command protocol, incorporating parity data for integrity, command queuing, and direct memory access (DMA) management to optimize operations across volatile and non-volatile memory, ensuring efficient data processing and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple flash memory chips are used in a scale-out storage system, then storage capacity is increased, but overall durability and performance are reduced due to variability in individual chip conditions
Solution Approach 1:
The storage system is divided into multiple independent flash memory chips (first flash memory chip, second flash memory chip, etc.), each with its own controller. This segmentation allows the system to scale capacity by adding more chips while managing individual chip variability through separate control and status monitoring.
Solution Approach 2:
Each flash memory chip includes a status register that provides feedback information about the chip's operating state, health, and performance. The controller reads these status registers to monitor individual chip conditions and adjust operations accordingly, ensuring overall system reliability despite variations in individual chip states.
2Quantity of substance
If multiple flash memory chips are used in a scale-out storage system, then storage capacity is increased, but processing speed is reduced due to variability in individual chip conditions
Solution Approach 1:
The storage system is divided into multiple independent flash memory chips, each with its own controller and status register. This segmentation enables parallel processing operations across different chips, maintaining high processing speed while scaling capacity.
Solution Approach 2:
The controller dynamically adjusts operations based on real-time status information from each chip's status register. When variability in chip conditions is detected, the controller can redistribute workloads, adjust timing, or use alternative chips to maintain optimal processing speed.
3Reliability
If a new command protocol with parity data and command queuing is implemented, then data integrity and command management are improved, but device complexity is increased
Solution Approach 1:
A status register acts as an intermediary between the flash memory chip and the controller, providing structured feedback information about chip state, command execution status, and error conditions. This intermediary simplifies the command protocol by providing a standardized interface for status reporting and error handling.
Solution Approach 2:
The patent replaces complex mechanical or procedural error handling with a digital status register system that automatically reports chip states and command execution results. This substitution reduces the need for complex control logic and manual error checking in the command protocol.
Data Source
AI summary
A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.