Scaled FET Gate Structure With Larger Contact Landing Area
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Solution Overview
Problem
Conventional lithographic patterning techniques for defining gate critical dimension in RFIC chips are limited, leading to small gate contact landing areas and potential voids or defects during replacement metal gate processing, which hinders the scaling of fin-type FETs with reduced effective gate lengths.
Innovation Solution
A semiconductor structure with a gate structure having a first portion proximal to the channel region and a second portion distal to it, featuring a conformal gate dielectric layer and a gate conductor layer, along with gate sidewall spacers to isolate the gate structure from source/drain regions, allowing for a scaled effective gate length that reduces overlap capacitance and enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning techniques are used to define gate critical dimension, then the gate structure can be formed, but the gate contact landing area becomes too small and voids or defects form during replacement metal gate processing
Solution Approach 1:
The gate structure is divided into two distinct portions: a first portion with a first critical dimension over the channel region, and a second portion with a second critical dimension that is larger than the first. This segmentation allows the gate to have a smaller effective gate length for reduced overlap capacitance while maintaining a larger contact landing area for reliable metal gate filling, thereby resolving the contradiction between manufacturing precision and reliability.
2Object-generated harmful factors
If the gate critical dimension is scaled down to reduce effective gate length, then overlap capacitance is reduced, but the gate opening becomes too small to fill with replacement metal gate without voids or defects
Solution Approach 1:
The gate structure is segmented into a first portion extending over the channel region with a first critical dimension, and a second portion adjacent to the first portion with a second critical dimension larger than the first. This allows the effective gate length to be reduced (lowering overlap capacitance) while the second portion provides a larger opening for defect-free metal gate filling.
Solution Approach 2:
Different portions of the gate structure have different critical dimensions tailored to their specific functions: the first portion has a smaller critical dimension to reduce overlap capacitance, while the second portion has a larger critical dimension to ensure proper metal gate filling. This local differentiation resolves the contradiction between reducing harmful capacitance effects and maintaining manufacturability.
3Length of moving object
If the gate critical dimension is reduced, then the effective gate length is reduced for improved performance, but the gate contact landing area becomes insufficient
Solution Approach 1:
The gate structure is divided into a first portion with a first critical dimension that determines the effective gate length, and a second portion with a second critical dimension that provides the contact landing area. By segmenting the gate, the effective gate length can be reduced for improved device performance while the second portion maintains a sufficient landing area for reliable electrical contact.
Solution Approach 2:
The gate structure extends in multiple dimensions: the first portion provides the critical dimension for gate control over the channel, while the second portion extends adjacent to it to provide additional area for contact landing. This dimensional extension allows simultaneous optimization of both gate length and contact area.
Data Source
AI summary
A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.