Scaler Dynamic Frame Rate Conversion for Display Synchronization
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Solution Overview
Problem
Existing data processing methods fail to dynamically convert input image signals with unsupported frame rates to frame rates compatible with display panels while maintaining low latency.
Innovation Solution
A scaler with an input interface, output vertical synchronization pulse generating circuit, and data buffer circuit is used to generate multiple output vertical synchronization pulses and frames, increasing the frame rate of the output image signal to match the display panel's supported rates by adjusting the timing of these pulses and frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the scaler operates in frame sync mode with synchronous Vsync generation, then low latency and synchronization are ensured, but the output frame rate cannot be adjusted to match display panel requirements when input frame rate is unsupported
Solution Approach 1:
The patent implements dynamic frame rate conversion by allowing the scaler to operate in both frame sync mode (for latency-sensitive operations) and frame rate conversion mode (for compatibility with different display panels). The system dynamically switches between these modes based on the input frame rate and display panel requirements, resolving the contradiction between maintaining synchronization and adapting to different frame rates.
Solution Approach 2:
The patent changes the operational parameters of the scaler by introducing a frame rate conversion mechanism that can transform the output frame rate while maintaining synchronization. By adjusting the frame rate conversion ratio and timing parameters, the system can match the output frame rate to display panel requirements without sacrificing synchronization reliability.
2Adaptability or versatility
If frame rate conversion is performed to match display panel requirements, then compatibility is improved, but latency may increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating the frame rate conversion ratio and preparing timing information before the actual frame rate conversion occurs. The scaler maintains a buffer of input frames and pre-determines when output frames should be generated, allowing the conversion to happen with minimal delay while maintaining synchronization with the display panel.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining continuous frame rate conversion operation without interruption. The scaler continuously processes input frames and generates output frames at the required rate, avoiding idle periods or interruptions that would increase latency. The frame buffer circuit continuously stores and manages frames, ensuring smooth transition and minimal delay.
3Productivity
If multiple output frames are generated from a single input frame through frame rate conversion, then the output frame rate increases to match display requirements, but the complexity of the data processing increases
Solution Approach 1:
The patent introduces an intermediary frame buffer circuit that simplifies the data processing complexity. This buffer circuit acts as a mediator between the input frame source and the output frame generator, managing the storage and retrieval of frames during rate conversion. By using this intermediary structure, the system can generate multiple output frames from input frames without significantly increasing the complexity of the core processing logic.
Data Source
AI summary
A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.