Scan-Based IC Clock Frequency Divider Phase Synchronization
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Solution Overview
Problem
The existing scan test methods for logic circuit units with clock frequency dividers face inefficiencies in generating scan patterns and timing adjustments due to skew between clock signals and divided clock signals, making it difficult to synchronize clock frequencies effectively.
Innovation Solution
A scan-based integrated circuit design that includes a clock generator producing multiple clock signals using a reference clock signal and a synchronous clock circuit unit, where the phase relationship of the clock signals is synchronized during the transition from scan shift mode to launch and capture mode using a clock gating circuit, ensuring all clock signals are synchronized within the scan shift and launch and capture modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiplexer is provided on the output end of the clock frequency divider to perform delay test, then the scan test can be performed, but the generation of scan pattern becomes extremely inefficient and timing adjustment becomes difficult due to skew between clock signal and divided clock signal
Solution Approach 1:
The patent applies preliminary action by setting up the phase relationship of clock signals using the reference clock signal just after the scan shift mode is transferred to the launch and capture mode. This preliminary phase synchronization ensures that clock signals are synchronized before the actual delay test begins, avoiding the inefficiency of pattern generation that occurs when using a multiplexer during the test itself.
Solution Approach 2:
The patent introduces a clock gating circuit as an intermediary between the clock frequency divider and the scan chain. This clock gating circuit generates synchronized clock signals by using the reference clock signal to control the phase relationship, thereby mediating the timing between the divided clock signal and the scan chain without requiring a multiplexer.
2Adaptability or versatility
If a multiplexer is used to select between clock signal and divided clock signal, then delay test can be performed, but timing adjustment becomes difficult due to skew between signals
Solution Approach 1:
The clock gating circuit serves as an intermediary that generates synchronized clock signals by controlling the phase relationship using the reference clock signal. This intermediary approach provides precise timing control without the skew problems associated with multiplexer-based signal selection.
Solution Approach 2:
The patent changes the parameter of phase relationship by setting it up using the reference clock signal just after mode transfer. This parameter change ensures that the clock signals maintain synchronized phases throughout operation, eliminating the timing adjustment difficulties that would otherwise require precise manual calibration.
3Adaptability or versatility
If clock frequency divider is used to generate divided clock signal, then multiple frequencies can be obtained, but phase synchronization between clock signals becomes problematic
Solution Approach 1:
The clock gating circuit acts as an intermediary that maintains stable phase relationships between the reference clock signal and the divided clock signal. It uses the reference clock signal to control the phase of generated clock signals, ensuring stability despite frequency division.
Solution Approach 2:
The patent dynamically changes the phase relationship parameter by setting it up using the reference clock signal just after mode transfer. This ensures that even when frequency division occurs, the phase relationship remains stable and synchronized throughout operation.
Data Source
AI summary
An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which are synchronized with one another and are provided with mutually different frequencies. The synchronous clock circuit unit includes synchronous clock circuits to which the first clock signal, the second clock signal, and the third clock signal are inputted, respectively. The synchronous clock circuits are scanned by use of the first clock signal, the second clock signal, and the third clock signal.