Scan Cell Power Sensitivity Identification for IC Testing
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Solution Overview
Problem
Scan-based testing of integrated circuits leads to excessive power consumption due to high switching activity during test operations, which can damage devices and result in misidentification of functional circuits as defective.
Innovation Solution
The method involves computing signal probability values and toggling rate reduction values for scan cells, identifying power-sensitive scan cells, and inserting logic to freeze their parallel outputs during the scan shift process, thereby reducing power consumption by blocking transitions from reaching the functional logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based testing is performed with high switching activity, then test coverage and fault detection capability are improved, but power consumption increases excessively causing device damage and test inaccuracies
Solution Approach 1:
The patent segments the scan chain into multiple groups and selectively activates only the necessary segments during testing. This segmentation allows the test system to maintain comprehensive fault detection capability while reducing the number of active scan cells, thereby lowering power consumption and preventing device damage during test operations
Solution Approach 2:
The patent dynamically changes the activation state of scan cells based on test requirements. By controlling the enable signals to scan cells, the system can adjust the number of active cells during different test phases, optimizing the balance between test coverage and power consumption to prevent excessive heating and test errors
2Ease of operation
If scan cells are activated during scan shifting, then test pattern loading is enabled, but excessive switching activity causes voltage droops and slower performance
Solution Approach 1:
The patent divides the scan chain into segments that can be independently controlled. During scan shifting operations, only the necessary segments are activated while others remain inactive, reducing overall switching activity and voltage droops while maintaining the ability to load test patterns efficiently
Solution Approach 2:
The patent applies partial action by activating only the minimum necessary scan cells required for the current test operation rather than all scan cells. This reduces unnecessary switching activity and voltage droops during scan shifting, improving chip performance while still enabling complete test pattern loading
3Reliability
If all scan cells are used during capture cycles, then complete functional logic testing is achieved, but excessive power consumption raises device temperature and causes misidentification of good devices
Solution Approach 1:
The patent applies local quality by selectively enabling only the scan cells that are necessary for testing specific functional logic blocks. Different functional blocks are tested with their required scan cells activated while other scan cells remain inactive, maintaining comprehensive functional testing capability while reducing overall power consumption and temperature rise that could cause false failures
Data Source
AI summary
Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified.