Scan Chain Cell Delay Testing via Internal Inversion
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Solution Overview
Problem
Conventional scan chain cells are inadequate for performing delay testing in complex integrated circuits due to their slow scan clock speed and small, weak gates, making it difficult to generate rapid signal transitions, especially in designs with small process sizes where variability between gates increases, leading to lower yields and the need for more significant testing efforts.
Innovation Solution
The integration of inverting circuitry, inverted value selecting circuitry, and output signal holding circuitry within scan chain cells, controlled by functional and test signals, allows for the generation of inverted signals and holding of signal values, enabling reliable delay testing without the need for rapid transition generation mechanisms, and can be shared among multiple cells to reduce control signal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If scan chain cells are used with slow scan clock for area saving and power saving, then area and power consumption are reduced, but the ability to generate rapid signal transitions for delay testing deteriorates
Solution Approach 1:
The scan chain cell incorporates a dual-mode clocking system that dynamically switches between scan clock mode (for testing) and functional clock mode (for normal operation). The clock selection logic enables the cell to adapt its operating characteristics based on the mode, allowing rapid transitions during delay testing while maintaining area and power efficiency during normal operation.
Solution Approach 2:
The invention changes the operational parameters of the scan chain cell by introducing a test mode that activates inverted value selecting circuitry and output signal holding circuitry. These parameter changes enable the cell to generate inverted signals rapidly and hold signals steady, providing the speed necessary for delay testing without permanently increasing the cell's area or power consumption.
2Area of moving object
If conventional scan chain cells are used with small gates for area saving, then area is reduced, but the strength and ability to drive rapid transitions deteriorates
Solution Approach 1:
The inverted value selecting circuitry acts as an intermediary mechanism that enables small gates to achieve strong driving capability during delay testing. By selectively activating the inverting circuitry and holding circuitry, the system compensates for the limited strength of small gates, allowing them to drive rapid transitions when needed without increasing their size.
3Speed
If multiple state holding elements are added to scan chain cell for rapid transition generation, then rapid transition capability is improved, but device complexity increases
Solution Approach 1:
The output signal holding circuitry is designed to serve multiple functions: it holds signals during delay testing, maintains state during functional operation, and enables rapid transitions when activated. This multi-functionality allows the circuit to achieve rapid transition capability without adding multiple dedicated state holding elements, thereby reducing overall device complexity.
4Ease of operation
If scan clock is used to shift signal values through scan chain, then signal values can be serially advanced, but the speed is too slow for delay testing
Solution Approach 1:
The inverting circuitry performs the signal transition preparation in advance by generating the inverted signal value before it is needed. The holding circuitry then maintains this pre-prepared signal ready for immediate output, eliminating the need to wait for slow scan clock progression. This preliminary action enables rapid transitions without sacrificing the ease of serial signal advancement.
Data Source
AI summary
A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.