Scan Chain Clock Control System for Dynamic Voltage Drop Reduction
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Solution Overview
Problem
Conventional scan chain control techniques in integrated circuits (ICs) lead to significant dynamic voltage drops and localized voltage hotspots due to simultaneous flip-flop operations within scan chains, increasing design complexity and requiring dedicated test controllers, which can be impractical for all ICs.
Innovation Solution
A clock control system that generates two clock signals for a single scan chain, ensuring flip-flop operations are mutually exclusive during the shift phase and potentially simultaneous during the capture phase, reducing dynamic voltage drops and eliminating the need for partitioning scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simultaneous flip-flop operations are performed in scan chains during testing mode, then testing functionality is achieved, but significant dynamic voltage drops and localized voltage hotspots occur
Solution Approach 1:
The scan chain is divided into multiple segments, each controlled by a separate clock gate. Different clock signals are applied to different segments, allowing staggered flip-flop operations that prevent simultaneous switching across the entire chain, thereby reducing dynamic voltage drops and voltage hotspots while maintaining testing functionality
Solution Approach 2:
Clock signals are applied periodically to different scan chain segments in a staggered manner. The clock gates control when each segment operates, creating a periodic pattern of flip-flop operations that distributes the switching activity over time, reducing peak current demand and associated voltage drops
2Object-affected harmful factors
If scan chains are partitioned to reduce voltage drops, then dynamic voltage drops are reduced, but device complexity increases due to dedicated test controllers
Solution Approach 1:
The clock gate circuitry is designed to be universal and reusable across multiple scan chain segments. The same clock gate structure and control logic can be replicated and applied to different segments, eliminating the need for dedicated complex test controllers for each partition while still achieving voltage drop reduction through staggered operations
Data Source
AI summary
A clock control system for a scan chain generates two clock signals. During a shift phase of a testing mode of the scan chain, one clock signal is an inverted version of the other clock signal. The clock control system provides the clock signal and the inverted clock signal to two different scan flip-flops of the scan chain, respectively. Each of the two scan flip-flops performs a flip-flop operation when the received clock signal transitions from a de-asserted state to an asserted state. Thus, the two flip-flop operations are mutually exclusive during the shift phase. As a result, a dynamic voltage drop across the scan chain during the shift phase is reduced.