Scan Chain Clock Gating for Lower-Power Semiconductor Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing scan test methods for semiconductor devices face challenges in reducing instantaneous power consumption during both shift and capture modes, leading to increased design optimization and power analysis time, especially with the growing scale of semiconductor devices.
Innovation Solution
A semiconductor device and method that divides the scan chain into multiple circuit blocks, using clock gating cells and temporary storage flip-flops to operate circuit blocks at different timings, reducing power consumption by limiting simultaneous activations to one block at a time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If many flip-flops are operated with a single scan clock, then the scan test can be performed efficiently, but the instantaneous power consumption increases
Solution Approach 1:
The scan chain is divided into multiple independent circuit blocks (first circuit block, second circuit block, etc.), each capable of being controlled separately. This segmentation allows selective activation of individual blocks during scan testing, preventing all flip-flops from operating simultaneously and thus reducing instantaneous power consumption while maintaining test coverage.
Solution Approach 2:
The patent introduces dynamic control mechanisms including selection circuits and control circuits that can activate different circuit blocks at different times based on test requirements. The system transitions from static simultaneous operation to dynamic sequential operation, where the control circuit generates control signals to enable/disable specific blocks, optimizing power consumption according to testing needs.
2Power
If the scan chain is divided into multiple circuit blocks with different timing clock supply, then instantaneous power consumption is reduced, but the test execution time increases
Solution Approach 1:
The control circuit operates in periodic cycles, sequentially activating different circuit blocks in repeated cycles. Each cycle tests one or more blocks, then transitions to the next block. This periodic operation allows the system to complete all tests eventually while maintaining low power consumption during each individual cycle, balancing time and power trade-offs.
Solution Approach 2:
The system performs preliminary setup by dividing the scan chain into blocks and pre-configuring the control circuit with the sequence of blocks to test. This preliminary organization allows efficient sequential testing without repeated reconfiguration, reducing the overall time penalty of block-by-block testing through systematic planning.
3Loss of time
If clock is supplied to each circuit block at the same time during shift mode, then the scan test completes quickly, but instantaneous power consumption cannot be reduced
Solution Approach 1:
The control circuit dynamically adjusts the timing of clock supply to different circuit blocks based on the test mode. During shift mode, the system can activate blocks sequentially rather than simultaneously, using control signals to gate the clock distribution. This dynamic timing control enables power reduction while maintaining test functionality.
Solution Approach 2:
The control circuit is pre-configured with the sequence and timing of block activation for shift mode testing. By having the preliminary test sequence ready, the system can efficiently execute blocks in an optimized order that balances completion time and power consumption, avoiding random or suboptimal timing patterns.
Data Source
AI summary
In scan testing of semiconductor devices, instantaneous power consumption in both shift and capture modes is efficiently reduced. The scan chain is provided with circuit blocks 1 to 4. Each of the temporary storage flip-flops F1 to F3 is connected between one of the two circuit blocks. Clock generating circuit 10 outputs a clock signal CLK used for the scan test. The clock gating cells GC1 to GC4 takes the clock signal CLK and provides the clock signals CLK1 to CLK4 to circuit blocks 1 to 4 and the clock signals CLK1 to CLK3 to the temporary storage flip-flops F1 to F3. The control circuit 20 controls the clock gating cells GC1 to GC4 so as to operate the circuit blocks 1 to 4 at differing timings from the input-side one by one and simultaneously operate each circuit block and a temporary storage flip-flop connected to the output of each circuit block.