Scan-Chain Clock Control for Power Supply Noise Balancing
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Solution Overview
Problem
Existing scan-chain testing methods fail to effectively address power supply noise during testing, leading to inefficiencies in test time, scalability, and increased costs due to the introduction of additional components or reduced power supply, which can impact the accuracy and efficiency of logic device testing.
Innovation Solution
Implementing a system that uses control circuitry to enable multiple clock signals during idle portions of the scan-chain test, balancing noise by providing additional clock signals to inactive devices within the same voltage domain, thereby offsetting noise without additional components or reduced power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal is gated or slowed down during transitional periods in scan-chain testing, then the testing process can transition between different parts of the test, but noise is created in the supply voltage driving the logic devices
Solution Approach 1:
The patent applies continuity of useful action by ensuring that at least one clock signal continues to drive logic devices during idle portions of scan-chain testing. Instead of completely gating the clock signal during transitions, the system maintains continuous clocking of active devices, thereby eliminating supply voltage noise while preserving testing efficiency and productivity.
2Object-affected harmful factors
If additional components are introduced to address power supply noise during testing, then noise can be reduced, but system complexity and cost increase
Solution Approach 1:
The patent applies self-service by utilizing existing clock signals and logic devices within the system to address power supply noise. Instead of introducing external noise reduction components, the system leverages its own clock infrastructure, enabling active devices to continue operating during idle portions and naturally eliminating supply voltage noise without additional hardware complexity.
3Ease of operation
If the clock signal is completely gated during idle portions, then testing can transition between parts, but test time increases and productivity decreases
Solution Approach 1:
The patent applies dynamics by implementing selective clock gating based on device activity state. The system dynamically adjusts clock signal delivery - maintaining continuous clocking for active logic devices during idle portions while allowing clock signals to be gated for inactive devices. This dynamic approach enables smooth test transitions between different testing phases without introducing additional test time delays.
Data Source
AI summary
In an embodiment, a system includes control circuitry to enable different clock signals. The control circuitry is configured to enable a first clock signal to drive a device-under-test coupled to a power supply. The first clock signal includes a first portion that includes a first set of clock cycles, a second portion that includes a second set of clock cycles, a third portion that includes a third set of clock cycles, a first idle portion between the first portion and the second portion, and a second idle portion between the second portion and the third portion. The control circuitry is further configured to, during the first and second idle portions, enable a second clock signal supplied to a different device coupled to the power supply.