Semiconductor Integrated Circuit Scan Chain Clock Selection for BIST Power Reduction
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Solution Overview
Problem
Current semiconductor integrated circuits face challenges in reducing power consumption during built-in self-test (BIST) operations, which can lead to increased power supply voltage drops and potential errors or noise during testing, especially when ordinary operations are performed in parallel with testing.
Innovation Solution
The semiconductor integrated circuit employs a logic circuit with multiple scan chains operating on different clock signals, a pattern generator, a compression circuit, a clock select circuit, and a test control circuit to selectively execute scan shift and capture operations on only the necessary scan chains, reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all scan chains operate simultaneously during BIST, then test coverage is improved, but power consumption increases causing voltage drops and noise
Solution Approach 1:
The patent divides scan chains into multiple groups (first scan chain group and second scan chain group) that operate at different times. The test controller executes scan shift operations on one group while performing capture operations on another group, thereby segmenting the simultaneous operation into sequential groups to reduce peak power consumption while maintaining comprehensive test coverage.
Solution Approach 2:
The patent implements periodic alternation between operating on different scan chain groups. The test controller periodically switches between executing scan shift operations on the first group and capture operations on the second group, creating a rhythmic operation pattern that distributes power consumption over time rather than concentrating it all at once.
2Productivity
If multiple scan chains operate in parallel, then testing efficiency is improved, but power supply voltage stability deteriorates
Solution Approach 1:
The patent segments scan chains into distinct groups that are activated at different times. By controlling the test controller to operate on one group during scan shift and another group during capture operations, the system maintains high testing efficiency through parallel group operations while preventing voltage instability by avoiding simultaneous activation of all scan chains.
Solution Approach 2:
The patent introduces dynamic control of scan chain operation states through the test controller, which adaptively switches between different operational modes (scan shift on first group, capture on second group). This dynamic state management allows the system to optimize both testing efficiency and voltage stability by adjusting which groups are active at any given moment.
3Reliability
If comprehensive testing is performed, then fault detection capability is improved, but power consumption increases causing noise interference
Solution Approach 1:
The patent segments the testing process into distinct phases operating on different scan chain groups. The test controller executes comprehensive fault detection by systematically testing all scan chains through alternating operations on the first and second groups, but reduces noise interference by ensuring that not all scan chains are active simultaneously, thereby distributing the harmful electrical noise over time.
Solution Approach 2:
The patent employs periodic switching between testing different scan chain groups to achieve comprehensive fault detection. The test controller periodically alternates between scan shift operations on one group and capture operations on another, ensuring all chains are thoroughly tested while the periodic nature of the operation prevents accumulation of noise and reduces instantaneous noise interference.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.