Scan Chain Clock Skew Circuitry for Peak Power Reduction
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Solution Overview
Problem
Scan design in digital circuits faces peak power issues during scan shift, leading to supply voltage noise and timing problems due to excessive transitions, which can cause hold-time violations and incorrect test decisions.
Innovation Solution
Implementing a chip with first and second scan chain segments and providing first and second test clock signals, where the second test clock signal is skewed with respect to the first during scan input periods and aligned during capture periods, using circuitry with delay circuits and multiplexers to manage clock skew and reduce concurrent scan shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple scan chains operate in parallel during scan shift, then test time is reduced, but peak power consumption increases due to excessive transitions
Solution Approach 1:
The scan chains are divided into groups that operate sequentially rather than all in parallel. The method segments the test process into multiple phases where different groups of scan chains are activated at different times, reducing the number of simultaneous transitions while maintaining overall test throughput.
Solution Approach 2:
The scan shift operation is performed periodically across different groups of scan chains. Instead of all chains shifting simultaneously, the method uses periodic activation where Group 1 shifts during one period, Group 2 shifts during the next period, and so on, creating a rhythmic pattern that limits peak power while maintaining productivity.
2Productivity
If scan chains are loaded simultaneously, then test efficiency is improved, but supply voltage noise increases due to excessive transitions
Solution Approach 1:
Scan chains are segmented into multiple groups that are loaded in sequential batches rather than all at once. This segmentation distributes the transition activity over time, preventing the simultaneous switching that causes supply voltage noise while preserving test efficiency through parallel processing of multiple groups.
Solution Approach 2:
The method performs preliminary scheduling of scan chain groups to determine which groups will be loaded at each time step. This preliminary action allows the system to prepare and execute loads in a controlled sequence that avoids noise-causing simultaneous transitions while maintaining efficient test throughput.
3Device complexity
If clock skew is not used, then circuit complexity is reduced, but hold-time violations occur during scan shift
Solution Approach 1:
The clock signal distribution is made dynamic through the use of multiplexers that can switch between different clock phases. During scan shift operations, the multiplexers dynamically select clock phases that provide the necessary skew for different scan chain groups, while during normal operation they provide synchronized clocks, thus adapting the timing behavior to operational requirements without permanent complexity.
Solution Approach 2:
Multiplexers are introduced as intermediary elements between the clock source and scan chain registers. These intermediaries selectively apply different clock phases to different groups of scan chains, providing the necessary timing skew to prevent hold-time violations during scan shift while maintaining simple synchronized operation during normal mode.
4Productivity
If all scan chains shift at the same time, then test throughput is maximized, but timing problems such as hold-time violations occur
Solution Approach 1:
Scan chains are segmented into multiple groups that shift in sequential batches. This segmentation maintains high throughput by keeping multiple groups active across different time periods while preventing timing problems by ensuring that not all chains shift simultaneously, thus avoiding the race conditions that cause hold-time violations.
Solution Approach 2:
The scan shift operation uses periodic activation of different scan chain groups. Group 1 shifts during the first period, Group 2 during the second period, and so on, creating a periodic pattern that maintains overall throughput while eliminating simultaneous transitions that cause timing violations. This periodic approach distributes the load evenly over time.
Data Source
AI summary
In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.