Scan Chain Diagnosis-Driven Compaction for IC Test Resolution
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Solution Overview
Problem
As integrated circuit complexity increases, scan chain defect diagnosis becomes more time-consuming and impractical due to the ratio of logic to be tested per pin and the volume of scan test data, which consumes Automatic Test Equipment (ATE) time and memory resources, and test compression techniques render failing scan cells less observable, making it difficult to identify failing scan chains from compacted test responses.
Innovation Solution
A computing system implementing an automatic test pattern generation tool performs scan chain diagnosis-driven compaction, determining locations of sensitive and unknown bits in scan chains through fault simulation, and generates a configuration for a compactor to compact test responses based on these locations, thereby optimizing test response compaction and observation sites.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If test compression techniques are applied to reduce ATE memory consumption and speed up test time, then test throughput is improved, but failing scan cells become less observable and diagnosis resolution deteriorates
Solution Approach 1:
The patent segments scan chains into multiple groups and applies different compaction settings to each group. By dividing the scan chains into segments (groups with different observation sites), the system can compact test responses more aggressively while maintaining observability of failing cells within each segment. This segmentation allows parallel processing of different scan chain groups, improving test throughput without sacrificing diagnosis resolution for any individual group.
Solution Approach 2:
The patent applies local quality by setting different compaction configurations for different groups of scan chains based on their specific characteristics. Each group can have optimized compaction settings that preserve the necessary observability for that particular group while allowing more aggressive compaction for other groups. This localized approach ensures that diagnosis resolution is maintained where needed while maximizing overall test throughput.
2Reliability
If the number of suspected defects increases, then more thorough testing is performed, but the physical failure analysis process becomes more onerous and time-consuming
Solution Approach 1:
The patent performs preliminary defect diagnosis through fault simulation and test response analysis before the physical failure analysis step. By using compaction settings that preserve observability of failing scan cells, the system can preliminarily identify and isolate suspected defects with high accuracy. This preliminary action reduces the number of suspected defects that require physical failure analysis, thereby reducing the time and effort required for the onerous PFA process while maintaining thorough defect identification.
3Adaptability or versatility
If integrated circuit complexity increases, then more logic is tested per pin, but the volume of scan test data consumes more ATE time and memory resources
Solution Approach 1:
The patent merges test responses from multiple scan chains through compaction. By combining test data from different scan chains into compacted responses, the system reduces the overall volume of scan test data that needs to be stored and processed by ATE. The merging is performed in a way that preserves the ability to identify failing scan cells through the compaction process, thus maintaining adaptability to test complex circuits while reducing data volume consumption.
Solution Approach 2:
The patent transforms the test data from a high-dimensional space (individual scan cell responses) to a lower-dimensional space (compacted test responses). By applying compaction, the system reduces the dimensionality of the test data volume while maintaining the essential information needed for defect diagnosis. This dimensional transformation allows the system to handle increased circuit complexity without proportionally increasing ATE memory resources.
Data Source
AI summary
This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.