Scan Chain Compressor-Decompressor for Multi-Power Domain ATPG
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Solution Overview
Problem
Existing techniques for testing integrated circuits are inefficient due to the need to apply multiple voltage stacks across different power domains, leading to increased test time and the inability to perform automated test pattern generation (ATPG) testing on all power domains.
Innovation Solution
The implementation of a scan chain compressor-decompressor pair with multiplexers and bypass circuits allows for selective testing of power domains at different voltage levels, enabling efficient testing by bypassing unnecessary domains and optimizing voltage usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple voltage stacks are applied to test all power domains at different voltage levels, then comprehensive testing coverage is achieved, but test time increases significantly
Solution Approach 1:
The power domains are segmented into different groups based on their voltage requirements. The scan chain is divided into multiple parallel scan chains, each assigned to specific power domain groups. This segmentation allows simultaneous testing of different power domains at their respective voltage levels, achieving comprehensive coverage without sequential testing delays.
Solution Approach 2:
The testing approach transitions from a single-dimensional sequential test (one voltage stack at a time) to a multi-dimensional parallel test structure. Multiple voltage stacks are applied simultaneously across different power domain groups through parallel scan chains, adding the dimension of parallelism to the testing process and dramatically reducing total test time.
2Reliability
If all power domains are tested at the highest voltage level (0.88v), then comprehensive functionality is verified, but testing of domains that don't require this voltage becomes inefficient
Solution Approach 1:
Each power domain group is assigned to a specific scan chain with a corresponding voltage stack tailored to that group's requirements. Power domains are tested at their minimum required voltage rather than a uniform high voltage across all domains. This local optimization of voltage application maintains reliability while improving testing efficiency for domains with lower voltage requirements.
3Use of energy by moving object
If voltage stack is reduced to 0.8v for low power mode testing, then energy consumption decreases, but testing speed must be reduced to ensure proper functionality
Solution Approach 1:
The scan chain is segmented into multiple parallel scan chains, each operating independently with its own voltage stack. This allows low-voltage scan chains to operate at reduced speed while high-voltage scan chains maintain full speed, eliminating the need to slow down the entire testing process when testing low-power domains.
Solution Approach 2:
Multiple parallel scan chains act as intermediaries between the test apparatus and different power domain groups. Each scan chain mediates the testing of its assigned power domains at appropriate voltage and speed levels, allowing simultaneous low-speed low-voltage testing and high-speed high-voltage testing without mutual interference.
4Device complexity
If a single scan chain is used to test all power domains, then device complexity is minimized, but the ability to perform simultaneous multi-voltage testing is lost
Solution Approach 1:
Multiple parallel scan chains are merged into a unified test architecture that shares common control logic and response capture mechanisms. This merging approach enables simultaneous multi-voltage testing while minimizing the duplication of control circuitry, achieving high throughput with controlled complexity.
Solution Approach 2:
The scan chain architecture is designed with universal components that can operate across multiple voltage domains. Control logic and response capture circuits are designed to handle multiple scan chains simultaneously, allowing the same hardware to perform both single-chain and multi-chain operations depending on the testing requirements.
Data Source
AI summary
Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.