Scan Chain Concurrent Signature Analysis for IC Fault Detection
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Solution Overview
Problem
Functional testing of integrated circuits faces challenges such as limited observability of internal faults due to insufficient automatic test equipment memory, increasing complexity and clock rates, and the inability to handle plesiochronous I/O pins, making it difficult to detect and diagnose faults effectively.
Innovation Solution
A method and circuit that utilize a scan chain with dual-mode storage elements to capture and shift out the internal state of an integrated circuit during functional testing, allowing for concurrent signature generation and reduced memory requirements, without needing high-speed or plesiochronous pins, by using a scan chain with separate functional and scan modes and a signature analyzer to compress data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional testing is performed to verify correct circuit operation, then circuit functionality is verified, but observability of internal faults is limited due to insufficient test equipment memory
Solution Approach 1:
A scan chain is introduced as an intermediary structure between the internal circuit nodes and the test equipment. The scan chain captures internal states through scan capture operations and transfers them serially to the test equipment, enabling observability of internal faults without requiring large test equipment memory.
Solution Approach 2:
The internal state of the circuit is copied into the scan chain storage elements during scan capture. This copy can then be read out serially and stored in test equipment memory, allowing functional verification while maintaining the ability to observe internal states.
2Adaptability or versatility
If the number of logic functions on the integrated circuit is increased, then circuit functionality is enhanced, but fault propagation to I/O pins becomes increasingly difficult
Solution Approach 1:
The scan chain serves as a direct intermediary path from internal logic nodes to the test equipment, bypassing the need for fault propagation through I/O pins. This allows observation of internal states regardless of the number of logic functions in the circuit.
3Speed
If internal clock frequencies are increased relative to I/O clock frequencies, then circuit speed is improved, but association of observed failures with proper internal clock cycles becomes increasingly difficult
Solution Approach 1:
The scan chain operates in periodic cycles: during functional clock cycles, the circuit operates at high speed; during scan clock cycles, the scan chain captures and shifts out internal states. This periodic operation maintains synchronization between the high-speed internal circuit and the slower test equipment.
4Difficulty of detecting and measuring
If scan chain is used to shift out test results, then observability of internal faults is improved, but functional testing is interrupted
Solution Approach 1:
The circuit operates in continuous functional mode during normal operation. Scan capture operations are performed periodically without stopping the functional clock, allowing both functional testing and fault observation to proceed continuously with minimal interruption.
Data Source
AI summary
A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during functional testing without interrupting the functional testing. The functional state may be captured by and shifted out of the scan chain concurrently with functional testing. The scan chain includes sequential elements, each having a functional state and a scan state that operate in parallel. The method and circuit may further include a signature analyzer for compressing the contents of the scan chain into a signature. The method and circuit may capture and compress multiple functional states into a combined signature.