Scan Chain Control Without a Dedicated Scan Enable Pin
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Solution Overview
Problem
The challenge in integrated circuit testing is the inefficiency and high cost associated with managing large volumes of scan data due to limited external pins, which prolongs test application times and compromises test coverage and reliability, especially in complex systems like automotive electronics.
Innovation Solution
A scan-compression architecture that eliminates the need for a dedicated scan enable pin by internally decoding the capture phase using an encoding of scan enable and masking signals, and employs on-chip comparator circuits and counter circuits to manage test phases efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated scan enable pin is used to control scan chain operations, then the scan chain can be reliably controlled, but the pin count increases and external interface complexity increases
Solution Approach 1:
The patent merges the scan enable signal with the scan data signal by using a single pin that carries both the scan data and the scan enable information encoded within the data bits. This is achieved by using specific bit patterns (e.g., all 1s or all 0s) to indicate scan enable state while other patterns indicate data loading or capture phases, thereby eliminating the need for a separate scan enable pin while maintaining reliable control.
Solution Approach 2:
The single pin serving dual purposes as both data input and scan enable control represents multi-functionality. The same physical pin performs multiple functions: carrying test data, indicating capture phase, and controlling scan chain operation, thereby reducing the overall pin count while maintaining all necessary control capabilities.
2Productivity
If scan compression is increased to reduce test data volume, then test time and cost decrease, but the complexity of managing scan data phases increases
Solution Approach 1:
The patent uses preliminary counter circuits that are pre-loaded with the number of shift cycles and capture cycles before testing begins. These counters automatically track the test phases without requiring external control signals, enabling the system to autonomously manage the transition between data loading, capture, and verification phases, thereby simplifying the management of compressed scan data.
Solution Approach 2:
The scan chain system becomes self-managing by using internally generated counter circuits and state encoding to automatically control the test phases. The system monitors its own state through the counter circuits and transitions between phases autonomously based on pre-loaded cycle counts, eliminating the need for external scan enable pins and complex external control logic.
3Productivity
If multi-site testing is implemented to increase throughput, then more devices can be tested simultaneously, but the volume of scan data to be delivered increases
Solution Approach 1:
The patent combines multiple scan chains into a unified testing architecture where multiple devices or dies are tested simultaneously using the same compressed scan interface. By merging the control and data management functions into a single integrated system with shared counter circuits and state encoding, the architecture can deliver scan data to multiple sites without proportionally increasing the data volume management complexity.
Data Source
AI summary
According to an embodiment, a method for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating a capture phase and a load/unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal; loading test parameters to the scan chain during the load/unload phase; operating the scan chain under functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.