Scan Chain Node Multiplexing for Faster IC Defect Localization
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Solution Overview
Problem
Existing integrated circuit testing methods, particularly using scan chains, face challenges in accurately identifying defects during the initial stages when yield is not secured, leading to inefficiencies in the testing process.
Innovation Solution
A test apparatus and method utilizing a multiplexer connected to elements in series, with a processor comparing data output from nodes against expected values to identify defects, reducing the time required to detect faulty elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain testing is used to test integrated circuits, then test coverage can be achieved, but testing accuracy is insufficient in the initial stage when yield is not secured
Solution Approach 1:
The patent divides the integrated circuit into multiple segments by inserting scan flip-flops at different locations. Each scan flip-flop independently tests a specific segment of the circuit, allowing precise identification of defective regions. This segmentation approach enables accurate defect localization without requiring exhaustive testing of the entire circuit, thereby improving test accuracy while reducing overall testing time.
Solution Approach 2:
The patent applies preliminary actions by performing initial defect detection using the scan flip-flops before conducting comprehensive functional testing. The scan flip-flops are configured to detect potential defects early in the testing process, allowing defective circuits to be identified and excluded from further time-consuming test sequences, thus reducing total testing time while maintaining accuracy.
2Measurement precision
If comprehensive testing is performed on all elements, then defect detection accuracy improves, but testing time increases significantly
Solution Approach 1:
The integrated circuit is divided into multiple testable segments using scan flip-flops positioned at strategic locations. Each flip-flop independently monitors a specific segment, enabling precise defect identification without requiring complete testing of all circuit elements. This segmentation maintains high defect detection accuracy while significantly reducing the number of test operations required, thereby improving testing efficiency.
Solution Approach 2:
The patent applies partial action by performing targeted testing on specific circuit segments rather than comprehensive testing of all elements. The scan flip-flops are configured to test only the portions of the circuit where defects are most likely to occur or where critical functionality exists, achieving sufficient defect detection accuracy with reduced testing effort and improved productivity.
3Quantity of substance
If scan flip-flops are connected in series to form a scan chain, then test coverage is achieved, but the ability to identify specific defective elements is reduced
Solution Approach 1:
The scan chain is segmented into multiple independent test groups, with each scan flip-flop responsible for testing a specific circuit segment. This segmentation allows the test coverage to be maintained across the entire circuit while simultaneously improving defect localization capability, as each flip-flop's test results directly indicate the status of its associated segment.
Solution Approach 2:
The scan flip-flops act as intermediaries between the test input and the circuit elements being tested. Each flip-flop captures and holds test data from its associated segment, serving as a mediator that enables both comprehensive test coverage and precise defect identification. The flip-flops translate the test signals into localized defect information, resolving the contradiction between coverage and localization.
Data Source
AI summary
A test apparatus includes an input terminal, a first multiplexer, a plurality of first elements connected in series between the input terminal and the first multiplexer, and a processor. The first multiplexer is connected to each of a plurality of nodes between the plurality of first elements, and the processor is connected to the input terminal and to the first multiplexer. The processor inputs data to the plurality of first elements through the input terminal. The plurality of first elements outputs at least a portion of a plurality of pieces of data through the plurality of nodes between the elements to the first multiplexer. The processor may thereby determine whether a defect has occurred in any of the plurality of first elements by comparing data, output from the multiplexer, with an expected output value.