Scan Chain Defect Location Using Last State Transition Capture

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Solution Overview

Problem

Existing methods for testing digital logic in complex semiconductor integrated circuits face challenges in efficiently locating and analyzing defects in scan chains, particularly when a fault in the scan chain path causes extensive non-deterministic data states, leading to the need for recording and analyzing millions of test failure data values.

Innovation Solution

An apparatus that dynamically captures the last data state transition by recording the bit positions of the last '1' or '0' shifted out of a scan chain, using a counter and registers coupled with magnitude comparators to identify the approximate location of a stuck-at defect without requiring extensive data capture and analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If extensive data recording and analysis is performed to locate scan chain defects, then measurement precision is improved, but loss of time and productivity deteriorate

Engineering Contradiction:
Improvedefect location precisionVSAvoidtest analysis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts only the critical information needed for defect localization - specifically the bit position of the last valid data state - from the complete test data stream. By recording only this extracted parameter rather than analyzing all millions of test failure data values, the system achieves accurate defect location while dramatically reducing analysis time and computational resources required.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If extensive data recording is performed to capture all test failure data values, then measurement precision is improved, but device complexity and data storage requirements worsen

Engineering Contradiction:
Improvedefect location precisionVSAvoiddata capture and analysis system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system extracts only the essential parameter - the bit position indicator of the last valid data state - from the complex test data stream. This extraction approach maintains defect localization precision while avoiding the complexity of capturing, storing, and analyzing complete test failure data sets.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses a simplified copy of the essential information (bit position of last valid state) rather than copying the entire test data set. This minimal copy contains sufficient information for defect localization without replicating the complexity and storage requirements of complete test data.

Inventive Principle:
Principle #26Copying

3Measurement precision

If complete test data analysis is performed, then measurement precision is improved, but productivity deteriorates

Engineering Contradiction:
Improvedefect location precisionVSAvoidtest execution efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts only the critical bit position information from the test data stream, enabling rapid defect localization without performing exhaustive analysis of complete test data. This extraction method maintains measurement precision while dramatically improving test execution efficiency and productivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7650547B2Apparatus for locating a defect in a scan chain while testing digital logic
Publication Date: 2010.01.19 ADVANTEST CORP
  • US7650547B2 patent drawing
  • US7650547B2 patent drawing
  • US7650547B2 patent drawing

AI summary

An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.