Scan Chain Circuitry for At-Speed Delay Fault Testing
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Solution Overview
Problem
Conventional scan chain testing methods for integrated circuits, particularly programmable logic device integrated circuits, face challenges in achieving complete test coverage due to difficulties in generating launch pulses and requiring precise control of timing signals, which can be costly and complex.
Innovation Solution
The implementation of scan chain circuitry with a multiplexer-based first logic circuit for forming scan chains and a second logic circuit that uses feedback paths and test enable signals to generate signal transitions, allowing for at-speed delay fault testing without relying on user logic, utilizing resources available in programmable logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional launch-off-capture techniques are used for TDF testing, then user logic can generate the launch pulse, but it may be difficult or impossible to produce the desired launch pulse from user logic in some integrated circuits, leading to incomplete test coverage
Solution Approach 1:
A dedicated pulse generation circuit is introduced as an intermediary component between the scan chain and the logic under test. This circuit receives control signals from the test equipment and autonomously generates the required launch pulses, eliminating the need for user logic to perform this function and ensuring consistent pulse generation across all test scenarios
Solution Approach 2:
The scan chain circuitry is enhanced with self-service capabilities through dedicated control logic that automatically generates launch pulses and manages timing sequences. This self-service mechanism allows the test circuitry to operate independently without relying on user-defined logic to produce critical test signals
2Adaptability or versatility
If conventional launch-off-shift techniques are used with high speed scan enable signal, then better test coverage can be achieved, but precise control of scan enable and clock signals is required, which can require costly high speed test equipment or complex on-chip test circuitry
Solution Approach 1:
The scan enable signal generation and clock signal control are merged into a unified control mechanism within the scan chain circuitry. A single control logic unit manages both signal sequences, ensuring precise timing relationships without requiring separate complex control circuits or external high-speed equipment
Solution Approach 2:
Feedback mechanisms are implemented within the scan chain control logic to automatically adjust and maintain precise timing relationships between scan enable and clock signals. The control circuit monitors signal transitions and dynamically synchronizes timing sequences, eliminating the need for external timing calibration equipment
3Measurement precision
If high speed test equipment is used for precise timing control, then adequate timing control can be achieved, but the cost increases significantly
Solution Approach 1:
The scan chain circuitry incorporates self-service timing control mechanisms that automatically generate and synchronize critical test signals. Dedicated control logic within the chip autonomously manages scan enable and clock signal timing, eliminating the need for external high-speed test equipment and significantly reducing testing costs
Solution Approach 2:
Dedicated control circuits are introduced as intermediaries between the test equipment and the logic under test. These intermediary circuits perform the complex timing control functions internally, requiring only simple control signals from external equipment and thereby reducing the sophistication and cost of required test equipment
Data Source
AI summary
Scan chain circuitry is provided for performing scan chain testing of integrated circuits. The integrated circuits being tested may include programmable logic. The scan chain circuitry may include scan chain cells. Each scan chain cell may have a first logic circuit that receives a scan enable signal. When the scan enable signal is asserted, the scan chain cells may be connected to form a scan chain for test data loading and unloading. Each scan chain cell may also include a second logic circuit. The second logic circuit in each scan chain cell may receive a test enable signal. Signal transitions may be created at the output of scan chain cells by loading the scan chain cells with data, deasserting the scan enable signal while the test enable signal is asserted, and applying a clock. At speed delay fault tests may be performed using the scan chain circuitry.