Scan Chain Verification Apparatus Using Delayed Clock Signals
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Solution Overview
Problem
Conventional design verification methods for semiconductor scan chains are inefficient due to the increased complexity and number of memory circuits, leading to prolonged calculation times and increased computational loads when verifying the correct coupling of scan chains during the design verification process.
Innovation Solution
A design verification support apparatus that calculates and stores delay times for clock signals reaching each memory circuit in the scan chain, allowing for selective calculation of output values based on the test pattern, thereby reducing the number of memory circuits that need to be processed at each cycle, and using precomputed delay times to supply clock signals to specific memory circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation is executed on all memory circuits at each clock cycle to verify scan chain coupling, then verification completeness is improved, but calculation time and computational load increase significantly
Solution Approach 1:
The patent extracts only the necessary memory circuits that actually change output values during shift operations from the complete scan chain. By identifying and processing only these relevant circuits based on test pattern analysis, the method reduces computational load while maintaining verification completeness for the actual test objectives.
Solution Approach 2:
The patent performs preliminary analysis of test patterns before execution to pre-identify which memory circuits will change output values at each clock cycle. This advance preparation allows the simulation to skip unnecessary calculations during actual execution, significantly reducing calculation time while ensuring all relevant circuits are verified.
2Measurement precision
If simulation is executed on all memory circuits at each clock cycle, then verification accuracy is improved, but productivity decreases due to prolonged simulation time
Solution Approach 1:
The patent extracts and processes only the subset of memory circuits that are relevant to the current test pattern and will actually change state. This selective approach maintains verification accuracy for the circuits that matter while improving simulation throughput by eliminating unnecessary calculations on circuits that remain unchanged.
Solution Approach 2:
The patent applies partial action by performing simulation only on the necessary portion of memory circuits rather than all circuits. By calculating output values only for circuits that will change state during the shift operation, the method achieves sufficient verification accuracy with reduced computational effort, thereby increasing productivity.
3Adaptability or versatility
If the number of memory circuits in scan chain increases with circuit scale, then functionality is improved, but calculation complexity increases
Solution Approach 1:
The patent extracts only the essential memory circuits that participate in state changes during test operations from the large-scale scan chain. By focusing computational resources on these extracted circuits rather than processing the entire scan chain, the method manages calculation complexity effectively while supporting large-scale circuit functionality.
Solution Approach 2:
The patent performs preliminary identification of relevant memory circuits based on test pattern analysis before simulation execution. This advance preparation creates a simplified view of the large scan chain, identifying only the circuits that need processing, thereby reducing calculation complexity while maintaining support for increased circuit scale and functionality.
Data Source
AI summary
A design verification support apparatus includes, a memory that stores circuit information and test pattern information, and a processor coupled to the memory. The processor performs a process including, acquiring the circuit information and the test pattern information from the memory, calculating a delay time occurring until the first clock signal reaches each of a plurality of memory circuits coupled in series and included in the scan chain from the clock source, based on the circuit information, selecting a first memory circuit whose first output value is to be changed by a shift operation among the plurality of memory circuits, based on the test pattern information at the cycle, and calculating the first output value of the first memory circuit when a second clock signal is supplied to the first memory circuit, the second clock signal being obtained by delaying the first clock signal by a delay time.