Scan Chain Diagnostic Using Functional Path Segmentation
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Solution Overview
Problem
Current integrated circuit (IC) defect analysis, particularly in scan chain diagnostics, faces challenges in pinpointing exact flip flop defects due to IC design limitations and computational intensity, leading to imprecise diagnosis and high computational load.
Innovation Solution
The method involves allocating flip flops into groups based on functional driver-load relationships, synthesizing scan chains, and forming functional shift registers into specific lengths to enhance diagnostic accuracy and efficiency by modeling scan chain connections within a circuit simulation environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional scan chain diagnostic methods are used, then the diagnostic process can be performed with existing IC design structures, but the precision of identifying faulty flip flops deteriorates due to IC design limitations and insufficiency of test data
Solution Approach 1:
The patent divides the scan chain into multiple segments by creating virtual scan chains that partition the original scan chain into distinct sections. Each virtual scan chain corresponds to a specific segment of the original scan chain, allowing independent analysis of each segment. This segmentation enables precise identification of faulty flip flops within specific segments, thereby improving diagnostic precision without requiring changes to the original IC design complexity.
Solution Approach 2:
The patent introduces virtual scan chains as intermediary structures that mediate between the original scan chain and the diagnostic process. These virtual scan chains are created by inserting virtual flip flops at strategic positions along the original scan chain, which act as mediators to enable more precise fault localization. The virtual scan chains provide additional test patterns and unload patterns that facilitate accurate diagnosis without modifying the physical IC design.
2Productivity
If scan chain diagnostics are performed on manufactured ICs with billions of devices, then defect detection can be conducted, but the computational intensity and time required deteriorate due to the need to simulate and analyze numerous test patterns
Solution Approach 1:
The patent segments the diagnostic process by creating multiple virtual scan chains that can be analyzed independently. Each virtual scan chain represents a segment of the original scan chain and can be tested with fewer test patterns. This segmentation reduces the total computational burden by allowing parallel analysis of multiple segments simultaneously, thereby improving diagnostic throughput while reducing the time required to complete the entire diagnostic process.
Solution Approach 2:
The patent applies partial action by testing only the necessary segments of the scan chain using virtual scan chains. Instead of testing the entire original scan chain with all possible test patterns, the virtual scan chains enable targeted testing of specific segments. This partial action approach reduces the number of computations required while maintaining sufficient diagnostic accuracy, thereby improving productivity and reducing computational time.
3Measurement precision
If weighted binary determination is used to identify failing flip flops, then the diagnostic process can be simplified, but the accuracy of pinpointing the exact defective flip flop deteriorates due to reliance on highest failure probability rather than precise location
Solution Approach 1:
The patent segments the scan chain into multiple virtual scan chains, each representing a distinct segment. By analyzing each segment independently through its own virtual scan chain, the system can precisely identify which segment contains the fault. This segmentation transforms the diagnostic process from a single-step probability-based determination to a multi-step process that systematically narrows down the fault location, thereby improving precision while maintaining operational simplicity through automated segment analysis.
Solution Approach 2:
The patent implements feedback by using the unload patterns from virtual scan chains to iteratively refine the fault location identification. The system analyzes the unload patterns from each virtual scan chain and uses this feedback information to determine which segment contains the faulty flip flop. This feedback mechanism enables precise fault location by continuously refining the diagnostic results based on the actual test data, thereby improving accuracy without significantly complicating the operational process.
Data Source
AI summary
An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.