Scan Chain Dispatcher Architecture for AFSM Test Pin Reduction
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Solution Overview
Problem
Existing testing architectures for Asynchronous Finite State Machine (AFSM) based IPs face inefficiencies due to the need for longer test patterns and higher pin overhead when using multiple scan chains, which complicates the testing process and increases test time.
Innovation Solution
A test system architecture that serially tests multiple AFSM circuits using multiple scan chains, with a dispatcher input interface and a dispatcher output interface, allowing for efficient selection and testing of individual scan chains without increasing the pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple scan chains are used to test multiple AFSM circuits, then test time is reduced, but pin overhead increases and device complexity increases
Solution Approach 1:
The patent combines multiple scan chains into a single unified scan chain architecture. Instead of having separate scan chains for each AFSM circuit, all scan chains are merged into one continuous chain that can be controlled to test individual circuits. This merging eliminates the need for multiple separate pin connections while maintaining the ability to test multiple circuits, thus reducing pin overhead while preserving test time efficiency.
Solution Approach 2:
The unified scan chain is designed with multi-functionality to serve multiple purposes. It can be configured to test any individual AFSM circuit or multiple circuits in sequence, making a single scan chain structure universal for testing all circuits. This multi-functional design allows the system to achieve the testing coverage of multiple scan chains without requiring multiple physical scan chain structures, thereby reducing device complexity and pin overhead.
2Productivity
If multiple scan chains are used to test multiple AFSM circuits, then test time is reduced, but managing physical links becomes more complex
Solution Approach 1:
The patent merges the management of multiple scan chains into a single unified management structure. Instead of independently managing multiple scan chains and their associated physical links, the unified scan chain architecture allows all testing to be managed through a single control interface. This consolidation significantly reduces the complexity of managing physical links and control signals while maintaining the productivity benefits of testing multiple circuits.
3Device complexity
If a single long scan chain is used, then pin count is reduced, but test time increases due to longer test patterns
Solution Approach 1:
The patent segments the single long scan chain into multiple logical sections, each corresponding to a specific AFSM circuit or group of circuits. Although physically implemented as a single scan chain, the architecture allows the test patterns to be selectively applied to different segments. This segmentation enables the system to use a single scan chain structure (reducing pin count) while maintaining the ability to test smaller circuit segments independently (reducing test time compared to testing the entire long chain as one unit).
Data Source
AI summary
According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.