Scan Chain ECO Netlist Modification for Register Up-Chaining
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Solution Overview
Problem
DFT engineers lack an efficient method to modify scan chains during Engineering Change Orders (ECOs) in ASIC designs, leading to issues like lower test coverage, higher test risk, and impact on back-end wiring performance due to mismanagement of register additions and deletions.
Innovation Solution
A system and method for performing scan chain ECO that includes input modules for receiving original netlists and register modification lists, a scan chain ECO module for modifying the netlist based on these inputs, and an output module for generating a modified scan chain netlist, ensuring efficient up-chaining and down-chaining of registers while preserving clock domain integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFT engineers manually modify scan chains during ECO using traditional methods, then the scan chain can be updated to accommodate register changes, but the process is time-consuming and error-prone, leading to lower test coverage and higher test risk
Solution Approach 1:
The system enables automatic scan chain ECO modification by having the processing unit autonomously read the ECO patch report, identify register changes, and perform up-chaining or down-chaining operations without requiring manual DFT engineer intervention. The system self-manages the entire workflow from reading the netlist to generating the modified scan chain configuration.
Solution Approach 2:
The patent replaces manual mechanical processes (DFT engineers physically examining and modifying scan chain configurations) with an automated electronic system that uses computer algorithms to process ECO reports and modify netlists automatically, significantly reducing time and human error.
2Manufacturing precision
If DFT engineers use ATPG tool to recheck and correct DFT DRC errors, then the design rule check errors can be corrected, but the process complexity increases and requires deep reference to established scan chain architecture
Solution Approach 1:
The system automatically performs DFT DRC error correction by reading the ECO patch report, identifying the affected registers, and executing the appropriate chaining operations without requiring external ATPG tool intervention or manual DFT engineer analysis of the scan chain architecture.
Solution Approach 2:
The patent extracts and isolates the specific error correction logic from the complex ATPG tool workflow, creating a dedicated automated module that handles only the scan chain ECO modification tasks, thereby simplifying the overall process while maintaining correction accuracy.
3Productivity
If newly added registers are discarded directly to simplify the ECO process, then the ECO modification becomes faster and simpler, but test coverage decreases and test risk increases
Solution Approach 1:
The system dynamically determines whether to perform up-chaining or down-chaining based on the register changes identified in the ECO patch report, automatically adapting the modification strategy to preserve test coverage while maintaining fast processing speeds through algorithmic decision-making.
Solution Approach 2:
The system automatically evaluates the ECO patch report and decides the appropriate chaining operation without requiring manual DFT engineer judgment, thereby maintaining both speed and test coverage through automated analysis and execution.
4Productivity
If already useless and removable registers are ignored directly during ECO, then the ECO process becomes faster, but back-end wiring performance and timing convergence are affected
Solution Approach 1:
The system dynamically evaluates each register's status and the ECO requirements to determine the optimal chaining strategy, automatically balancing speed improvements with the maintenance of wiring performance and timing convergence through algorithmic optimization.
Data Source
AI summary
The present application discloses a system and a method for performing a scan chain ECO, the method includes: receiving an original netlist input by a user as first input information, the original netlist contains original scan chain information; receiving a register modification list and a scan DEF file input by the user as second input information, wherein the register modification list is configured to indicate register information to be up-chained and/or register information to be down-chained; modifying the original netlist based on the first input information and the second input information, to complete up-chaining and/or down-chaining of a list of registers in the second input information to obtain a modified scan chain netlist; and receiving the modified scan chain netlist and returning the modified scan chain netlist to the user.