Scan Chain Clock Edge Inversion for Hold Timing Margin
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Solution Overview
Problem
Conventional high-voltage stress testing for semiconductor devices pushes them beyond their functional specifications, leading to timing issues and area overhead in scan chains, making it difficult to identify and fix hold timing violations, which can result in unsatisfactory operation and increased complexity.
Innovation Solution
Incorporating a clock inversion logic in flip-flops by adding a pin (CKT) to invert or keep the sampling edge based on a logic value, allowing for edge inversion between consecutive flip-flops, thereby providing a half-clock-period margin to prevent hold violations and reduce area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage stress testing is applied to screen infant mortality rate, then device reliability is improved, but timing violations and area overhead increase
Solution Approach 1:
The patent applies edge inversion to alternate flip-flops in the scan chain, where odd-positioned flip-flops sample on rising edges and even-positioned flip-flops sample on falling edges. This inversion strategy creates a half-clock-period margin that prevents hold timing violations during high-voltage stress testing, resolving the timing complexity issue while maintaining reliability screening capability
2Reliability
If conventional scan chain architecture is used, then device screening is achieved, but hold timing violations occur under stress conditions
Solution Approach 1:
The patent inverts the sampling edge for alternate flip-flops in the scan chain. By making odd-positioned flip-flops sample on rising edges and even-positioned flip-flops sample on falling edges, the invention creates a temporal buffer of half a clock period between consecutive sampling events. This buffer prevents hold timing violations that occur under high-voltage stress conditions, thereby maintaining timing precision while preserving screening capability
3Device complexity
If clock skew between test clock paths is present, then area penalty increases, but timing violations become harder to identify
Solution Approach 1:
The patent implements edge inversion at the flip-flop level rather than requiring complex clock path adjustments. This approach eliminates the need for additional clock buffering or skew compensation circuitry, thereby avoiding area overhead while making timing behavior predictable and easier to analyze during high-voltage stress testing
Data Source
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AI summary
The disclosure relates to a scan chain circuit (10) comprising cascaded flip-flops (101, 102, 103, 104, 105, 106) having a functional input node (D) and a test input node (TI) configured to be selectively (M, TE) coupled to logic circuitry (CL) at a clock edge time (tsetup, thold). A clock line (Clock) is provided configured to distribute one or more clock signals to the flip-flops in the chain (101, 102, 103, 104, 105, 106), wherein the flip-flops in the chain (101, 102, 103, 104, 105, 106) have active clock edges (CK) applied thereto at respective clock edge times. The chain of flip-flops (101, 102, 103, 104, 105, 106) comprise a set (101, 103, 105) of flip-flops configured to receive an edge inversion signal (TM) and to selectively invert their active clock edges (CKT) in response to the edge inversion signal (TM) being asserted.