Scan Chain Endpoint Clocking for Low-Power At-Speed Capture
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Solution Overview
Problem
Existing technologies face challenges in managing power consumption and handling timing exceptions during at-speed capture in scan chain testing, leading to reduced fault coverage and increased power consumption, particularly in large silicon chips with complex logic levels.
Innovation Solution
A control circuit and integrated circuit design that includes flip-flops, multiplexers, and clock gate circuits to generate independent clock and scan enable signals for endpoint scan flip-flops, allowing for selective control of clock gating and power management, thereby addressing multi-cycle and false paths without relying on SDC files.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating and power management techniques are applied during at-speed capture, then power consumption is reduced, but fault coverage and test effectiveness deteriorate
Solution Approach 1:
The scan chain is divided into multiple segments with independent clock control. Different segments can be clocked independently during at-speed capture, allowing clock gating to be applied to inactive segments while maintaining full fault coverage in active segments. This segmentation enables selective power management without compromising overall test effectiveness.
Solution Approach 2:
The patent implements dynamic clock gating control where clock signals are dynamically enabled or disabled based on the actual test requirements and timing exceptions detected during testing. The clock gating mechanism adapts in real-time to maintain fault coverage while minimizing power consumption, rather than using static power management approaches.
2Reliability
If timing exceptions from SDC files are considered during test generation, then timing constraints are satisfied, but device complexity and test generation complexity increase
Solution Approach 1:
The patent extracts timing exception information from SDC files and represents it in a simplified format that can be directly processed by ATPG tools. By taking out only the essential timing exception data and representing it in a compact manner, the complexity of test generation is reduced while still maintaining satisfaction of timing constraints.
Solution Approach 2:
The patent introduces an intermediary representation layer between the SDC file and the ATPG tool. This intermediary format serves as a mediator that translates complex timing exception specifications into a simpler form that ATPG tools can process efficiently, reducing the overall complexity of the test generation process while maintaining timing constraint satisfaction.
3Measurement precision
If independent clock control is implemented for endpoint flip-flops, then observability and controllability are enhanced, but device complexity increases
Solution Approach 1:
The patent implements a universal clock control mechanism where a single clock control unit can manage multiple endpoint flip-flops through a standardized interface. This multi-functional approach enhances observability and controllability of individual flip-flops while avoiding the need for separate complex control circuits for each flip-flop, thus limiting the increase in overall device complexity.
Data Source
AI summary
According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.