Semiconductor Fault Localization via Scan Chain Geometric Mapping
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Solution Overview
Problem
Current yield management systems are ineffective at locating design-introduced electrical faults in semiconductor wafers at geometries below 90 nm, as they lack the ability to geometrically pinpoint defects and cannot translate scan chain test failures into physical locations on the wafer.
Innovation Solution
A computer-implemented method that combines automatic test equipment failure data with layout information to determine the physical die location of electrically failing circuit structures, using novel data compression and parsing techniques to create a geometric database, and tracing components and wires to compute bounding boxes for fault localization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If scan chain testing is used to test high density semiconductor devices, then testability is improved, but the ability to geometrically locate defects is lost
Solution Approach 1:
The patent introduces an intermediary mapping system that connects scan chain test results to geometric locations on the wafer. This intermediary layer translates the abstract scan chain bit positions into concrete geometric coordinates by using the relationship between scan chain cells and their corresponding physical locations on the semiconductor die, thereby resolving the contradiction between testability and geometric location precision
Solution Approach 2:
The patent adds a new dimensional mapping from the one-dimensional scan chain sequence to the two-dimensional geometric plane of the wafer. By establishing this dimensional transformation through the mapping of scan chain bits to physical locations, the system maintains the simplicity of scan chain testing while gaining geometric location capability
2Reliability
If current yield management system tools are used, then general defect detection is possible, but design-introduced electrical faults cannot be localized
Solution Approach 1:
The patent applies local quality by focusing the analysis on specific regions of interest on the wafer where design-introduced faults are most likely to occur. By targeting particular geometric locations and circuit structures rather than treating the entire wafer uniformly, the system improves fault localization precision while maintaining reliable defect detection
Solution Approach 2:
The patent creates a virtual copy or representation of the wafer layout and circuit structure that can be searched and analyzed independently. This virtual model allows for precise localization of design-introduced faults without physically inspecting each region, enabling both reliable detection and precise localization
3Measurement precision
If production test data is stored in detail, then fault analysis accuracy is improved, but data storage requirements increase
Solution Approach 1:
The patent extracts only the essential information needed for fault analysis from the comprehensive production test data. By taking out and storing only the critical fault location data, geometric coordinates, and relevant test results rather than all raw test data, the system maintains fault analysis accuracy while significantly reducing data storage requirements
Solution Approach 2:
The patent performs preliminary processing and aggregation of test data during the testing process itself, organizing and pre-processing the data into a compact format that is ready for analysis. This preliminary action reduces the amount of data that needs to be stored and processed later, maintaining accuracy while reducing storage requirements
Data Source
AI summary
A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.