Scan Chain Flip-Flop Ordering Optimization for IC Design
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Solution Overview
Problem
In IC design, non-ideal ordering of flip-flops in scan chains leads to routing issues, timing violations, increased area costs, and prolonged timing closure schedules due to on-chip variations, which are exacerbated by suboptimal clock tree structures and scan chain configurations.
Innovation Solution
An IC design method that retrieves a clock tree structure with flip-flops and clock units, calculates branch levels, determines wire distances and clock skews, and updates the scan chain connection order to minimize costs by identifying a path with the lowest cost from an initial to a terminal point, optimizing the flip-flop arrangement in the scan chain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the scan chain connection order is not optimized, then the design process is simpler, but the area cost increases and timing violations occur
Solution Approach 1:
The patent changes the ordering parameter of flip-flops in the scan chain from arbitrary or default sequence to an optimized sequence determined by clock skew and wire distance calculations. This parameter optimization reduces area cost while maintaining design process automation, resolving the contradiction between simplicity and area efficiency.
2Productivity
If the scan chain connection order is not optimized, then the implementation is faster, but timing violations and routing issues occur
Solution Approach 1:
The patent performs preliminary calculations of clock skew and wire distance for all flip-flop pairs before determining the optimal scan chain ordering. This advance preparation ensures timing compliance is built into the design from the start, preventing timing violations while maintaining implementation speed through automated optimization.
3Device complexity
If on-chip variation effects are not considered, then the design process is simpler, but hold time violations become severe
Solution Approach 1:
The patent applies local quality optimization by considering on-chip variation effects specifically in the hold time analysis for each flip-flop pair. The cost function incorporates local variation characteristics to determine optimal scan chain ordering, ensuring hold time compliance without requiring complex global redesign.
4Area of stationary object
If the scan chain ordering is optimized, then area cost and timing closure duration are reduced, but the design process becomes more complex
Solution Approach 1:
The patent implements self-service automation where the design tool automatically performs clock skew calculation, wire distance measurement, cost function evaluation, and scan chain reordering without manual intervention. This automation handles the increased design process complexity internally while delivering optimized results that reduce area cost.
5Loss of time
If the scan chain ordering is optimized, then timing closure duration is reduced, but the design process becomes more complex
Solution Approach 1:
The patent replaces manual or iterative mechanical optimization processes with an automated computational system that calculates optimal scan chain ordering based on clock skew and wire distance metrics. This substitution eliminates time-consuming manual adjustments while managing design process complexity through systematic automation.
Data Source
AI summary
An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.