Scan-Chain Flip-Flop Resetting Without Dedicated Reset Networks
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Solution Overview
Problem
Traditional integrated circuit resetting methods require substantial area and power due to the presence of reset circuitry, leading to issues like current spikes and reset domain crossing, which complicates debugging and increases power consumption.
Innovation Solution
The proposed solution involves connecting flip-flops in a predefined series without a reset gate or associated circuitry, using a scan input gate and output gates to facilitate resetting, thereby reducing area and power consumption by eliminating dedicated reset networks and circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reset circuitry is used to reset integrated circuits, then resetting functionality is achieved, but area consumption and power consumption increase substantially
Solution Approach 1:
The patent extracts and removes the dedicated reset circuitry from the integrated circuit design. Instead of including traditional reset gates and associated circuitry for each flip-flop, the invention eliminates these components entirely and uses the existing scan chain infrastructure to achieve resetting functionality, thereby reducing area consumption while maintaining resetting capability
Solution Approach 2:
The patent makes the scan chain serve multiple functions: it performs both its traditional testing/debugging function and also provides resetting functionality. By utilizing the existing scan input gates and flip-flop structure for dual purposes, the invention eliminates the need for separate dedicated reset circuitry, achieving multi-functionality without additional area overhead
2Reliability
If conventional reset circuitry is used to reset integrated circuits, then resetting functionality is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the dedicated reset circuitry from the integrated circuit design. Instead of including traditional reset gates and associated circuitry for each flip-flop, the invention eliminates these components entirely and uses the existing scan chain infrastructure to achieve resetting functionality, thereby reducing area consumption while maintaining resetting capability
Solution Approach 2:
The patent makes the scan chain serve multiple functions: it performs both its traditional testing/debugging function and also provides resetting functionality. By utilizing the existing scan input gates and flip-flop structure for dual purposes, the invention eliminates the need for separate dedicated reset circuitry, achieving multi-functionality without additional area overhead
3Reliability
If conventional reset networks are used, then resetting is achieved, but current spikes and reset domain crossing issues occur
Solution Approach 1:
The patent extracts and removes the dedicated reset circuitry from the integrated circuit design. Instead of including traditional reset gates and associated circuitry for each flip-flop, the invention eliminates these components entirely and uses the existing scan chain infrastructure to achieve resetting functionality, thereby reducing area consumption while maintaining resetting capability
Solution Approach 2:
The patent uses the scan chain as an intermediary mechanism to perform resetting. Instead of directly activating reset gates that cause simultaneous switching and current spikes, the invention uses the sequential scan chain structure to gradually transition flip-flop states, with the scan output of one flip-flop feeding the scan input of the next, thereby mediating the reset process to avoid harmful current spikes and domain crossing issues
Data Source
AI summary
A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.