Scan Chain Clock Edge Inversion for Hold Violation Prevention
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Solution Overview
Problem
Conventional high-voltage stress testing for semiconductor devices is challenging due to hold timing violations in scan chain architectures, which are difficult to identify and fix, leading to area penalties and reduced design complexity, especially when operating beyond functional specifications.
Innovation Solution
The introduction of a clock inversion logic mechanism by adding a pin (CKT) to each flip-flop to keep or invert the sampling edge based on a logic value, allowing for edge inversion between consecutive flip-flops, thereby providing a half-clock-period margin to avoid hold violations and optimize shift operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional scan chain architecture is used for high-voltage stress testing, then testing capability is provided, but hold timing violations occur that are difficult to identify and fix
Solution Approach 1:
The patent introduces an intermediary buffer stage between consecutive flip-flops in the scan chain. This buffer acts as a mediator that absorbs timing variations and prevents hold violations from propagating through the chain during high-voltage stress testing, making the system more detectable and controllable.
Solution Approach 2:
The patent applies preliminary timing adjustment by inserting buffers before the hold violation problem occurs. The buffers are strategically placed in advance to pre-compensate for timing issues that would otherwise be difficult to detect during high-voltage operation.
2Reliability
If hold timing violations are addressed by adding buffers or custom flip-flops, then timing reliability is improved, but area overhead increases
Solution Approach 1:
The patent applies local quality by inserting buffers only at specific critical locations in the scan chain where hold violations are most likely to occur, rather than uniformly across all flip-flops. This targeted approach maintains timing reliability while minimizing overall area overhead.
3Reliability
If scan chain operates beyond functional specifications during HVST, then infant mortality screening is enhanced, but design complexity increases due to library characterization requirements
Solution Approach 1:
The buffer stages serve as intermediaries that decouple the scan chain operation from the strict timing requirements of the flip-flops. This allows the system to operate beyond functional specifications during HVST without requiring extensive library characterization, as the buffers absorb the timing variations.
Data Source
AI summary
The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted.